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參數(shù)資料
| 型號： | IDT72281L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SuperSync FIFO |
| 中文描述： | 先進(jìn)先出的CMOS SuperSync |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 277K |
| 代理商： | IDT72281L |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
24
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected fromany one device.
The exceptions are the
EF
and
FF
functions in IDT Standard mode and the
IR
and
OR
functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for
EF
/
FF
deassertion and
IR
/
OR
assertion to vary
Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing
EF
of every FIFO, and
separately ANDing
FF
of every FIFO. In FWFT mode, composite flags can be
created by ORing
OR
of every FIFO, and separately ORing
IR
of every FIFO.
Figure 23 demonstrates a width expansion using two IDT72281/72291
devices. D
0
- D
8
fromeach device forma 18-bit wide input bus and Q
0
-Q
8
from
each device forma 18-bit wide output bus. Any word width can be attained by
adding additional IDT72281/72291 devices.
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (
MRS
)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (
WEN
)
FULL FLAG/INPUT READY (
FF
/
IR
)
PROGRAMMABLE (
PAF
)
PROGRAMMABLE (
PAE
)
EMPTY FLAG/OUTPUT READY (
EF
/
OR
) #2
OUTPUT ENABLE (
OE
)
READ ENABLE (
REN
)
m
LOAD (
LD
)
IDT
72281
72291
EMPTY FLAG/OUTPUT READY (
EF
/
OR
) #1
PARTIAL RESET (
PRS
)
IDT
72281
72291
4675 drw 24
FULL FLAG/INPUT READY (
FF
/
IR
) #2
HALF-FULL FLAG (
HF
)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (
RT
)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D
0
- Dm
DATA IN
Dm
+1
- Dn
Q
0
- Qm
Qm
+1
- Qn
FIFO
#1
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| IDT72281L10PF | CMOS SuperSync FIFO |
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| IDT723612L15PQF | BiCMOS SyncBiFIFOO 64 x 36 x 2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72281L10PF | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72281L10PF8 | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72281L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP |
| IDT72281L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP |
| IDT72281L10TF | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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