參數(shù)資料
型號(hào)： IDT72281L
廠商： Integrated Device Technology, Inc.
英文描述： CMOS SuperSync FIFO
中文描述： 先進(jìn)先出的CMOS SuperSync
文件頁(yè)數(shù)： 4/26頁(yè)
文件大小： 277K
代理商： IDT72281L
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
4
PIN DESCRIPTION
Symbol
D
0
–D
8
MRS
Name
I/O
I
I
Description
Data Inputs
Master Reset
Data inputs for a 9-bit bus.
MRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program-
mable flag default settings, and serial or parallel programmng of the offset settings.
PRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programmng method (serial or parallel), and
programmable flag settings are all retained.
RT
asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the
EF
flag to
LOW (
OR
to HIGH in FWFT mode) temporarily and does not disturb the write pointer, program
mng method, existing timng mode or programmable flag settings.
RT
is useful to reread data from
the first physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
this pin functions as a serial input for loading offset registers
When enabled by
WEN
, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programmng, and when enabled by
SEN
, the rising edge of
WCLK writes one bit of data into the programmable register for serial programmng.
WEN
enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by
REN
, the rising edge of RCLK reads data fromthe FIFO memory and offsets from
the programmable registers.
REN
enables RCLK for reading data fromthe FIFO memory and offset registers.
OE
controls the output impedance of Q
n.
SEN
enables serial loading of programmable flag offsets.
During Master Reset,
LD
selects one of two partial flag default offsets (127 or 1,023 and determnes
the flag offset programmng method, serial or parallel.
After Master Reset, this pin enables writing to
and reading fromthe offset registers.
This pin must be tied to either V
CC
or GND and must not toggle after Master Reset.
In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or not the FIFO
memory is full. In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is
space available for writing to the FIFO memory.
In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO
memory is empty. In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there
is valid data available at the outputs.
PAF
goes LOW if the number of words in the FIFO memory is more than total word capacity of the
FIFO mnus the full offset value m which is stored in the Full Offset register. There are two possible
default values for m 127 or 1,023.
PAE
goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in
the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF
indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 9-bus
+5 Volt power supply pins.
Ground pins.
PRS
Partial Reset
I
RT
Retransmt
I
FWFT/SI
First Word Fall
Through/Serial In
Write Clock
I
WCLK
I
WEN
RCLK
Write Enable
Read Clock
I
I
REN
OE
SEN
LD
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
DC
FF
/
IR
Don't Care
Full Flag/
Input Ready
I
O
EF
/
OR
Empty Flag/
Output Ready
O
PAF
Programmable
Almost-Full Flag
O
PAE
Programmable
Almost-Empty Flag
O
HF
Q
0
–Q
8
V
CC
GND
Half-Full Flag
Data Outputs
Power
Ground
O
O
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參數(shù)描述
IDT72281L10PF 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72281L10PF8 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72281L10PFG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP
IDT72281L10PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP
IDT72281L10TF 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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