參數(shù)資料
型號(hào): IDT72281L
廠商: Integrated Device Technology, Inc.
英文描述: CMOS SuperSync FIFO
中文描述: 先進(jìn)先出的CMOS SuperSync
文件頁(yè)數(shù): 6/26頁(yè)
文件大?。?/td> 277K
代理商: IDT72281L
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
6
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: V
CC
= 5V
±
10%, T
A
= 0
°
C to +70
°
C; Industrial: V
CC
= 5V
±
10%, T
A
= -40
°
C to +85
°
C)
Commercial
Commercial & Industrial
(2)
IDT72281L10
IDT72291L10
Min.
2
10
4.5
4.5
3
0
3
0
3
0
10
10
10
0
3
0
2
2
5
12
60
IDT72281L15
IDT72291L15
Min.
2
15
6
6
4
1
4
1
4
1
15
15
15
0
4
0
3
3
6
15
60
IDT72281L20
IDT72291L20
Min.
2
20
8
8
5
1
5
1
5
1
20
20
20
0
5
0
3
3
10
20
60
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
LDS
t
LDH
t
RS
t
RSS
t
RSR
t
RSF
t
FWFT
t
RTS
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
HF
t
SKEW1
t
SKEW2
t
SKEW3
Parameter
Max.
100
6.5
10
6
6
6.5
6.5
6.5
6.5
16
Max.
66.7
10
15
8
8
10
10
10
10
20
Max.
50
12
20
10
10
12
12
12
12
22
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
Reset Pulse Width
(3)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Mode Select Time
Retransmt Setup Time
Output Enable to Output in Low Z
(4)
Output Enable to Output Valid
Output Enable to Output in High Z
(4)
Write Clock to
FF
or IR
Read Clock to
EF
or
OR
Write Clock to
PAF
Read Clock to
PAE
Clock to
HF
Skew time between RCLK and WCLK for
FF
/
IR
Skew time between RCLK and WCLK for
PAE
and
PAF
Skew time between RCLK and WCLK for
EF
/
OR
NOTES:
1. All AC timngs apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
3. Pulse widths less than mnimumvalues are not allowed.
4. Values guaranteed by design, not currently tested.
I
nput Pulse Levels
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 2
AC TEST CONDITIONS
* Includes jig and scope capacitances.
4675 drw 04
1.1K
30pF*
680
5V
D.U.T.
Figure 2. Output Load
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