參數(shù)資料
型號(hào)： IDT72281L
廠商： Integrated Device Technology, Inc.
英文描述： CMOS SuperSync FIFO
中文描述： 先進(jìn)先出的CMOS SuperSync
文件頁數(shù)： 10/26頁
文件大?。?/td> 277K
代理商： IDT72281L
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
10
SERIAL PROGRAMMING MODE
If Serial Programmng mode has been selected, as described above,
then programmng of
PAE
and
PAF
values can be achieved by using a
combination of the
LD
,
SEN
, WCLK and SI input pins. Programmng
PAE
and
PAF
proceeds as follows: when
LD
and
SEN
are set LOW, data on the
SI input are written, one bit for each WCLK rising edge, starting with the
Empty Offset LSB and ending with the Full Offset MSB. A total of 32 bits for
the IDT72281 and 34 bits for the IDT72291. See Figure 13,
Serial Loading
of Programmable Flag Registers
, for the timng diagramfor this mode.
Using the serial method, individual registers cannot be programmed se-
lectively.
PAE
and
PAF
can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When
LD
is LOW and
SEN
is HIGH, no serial write to the registers can
occur.
Write operations to the FIFO are allowed before and during the serial
programmng sequence. In this case, the programmng of all offset bits does
not have to occur at once. A select number of bits can be written to the SI
input and then, by bringing
LD
and
SEN
HIGH, data can be written to FIFO
memory via D
n
by toggling
WEN
. When
WEN
is brought HIGH with
LD
and
SEN
restored to a LOW, the next offset bit in sequence is written to the
registers via SI. If an interruption of serial programmng is desired, it is
sufficient either to set
LD
LOW and deactivate
SEN
or to set
SEN
LOW and
deactivate
LD
. Once
LD
and
SEN
are both restored to a LOW level, serial
offset programmng continues.
Fromthe time serial programmng has begun, neither partial flag will be
valid until the full set of bits required to fill all the offset registers has been
written. Measuring fromthe rising WCLK edge that achieves the above
criteria;
PAF
will be valid after two more rising WCLK edges plus t
PAF
,
PAE
will be valid after the next two rising RCLK edges plus t
PAE
plus t
SKEW2
.
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
If Parallel Programmng mode has been selected, as described above,
then programmng of
PAE
and
PAF
values can be achieved by using a
combination of the
LD
, WCLK ,
WEN
and D
n
input pins. For the IDT72281,
programmng
PAE
and
PAF
proceeds as follows: when
LD
and
WEN
are
set LOW, data on the inputs Dn are written into the Empty Offset LSB
Register on the first LOW-to-HIGH transition of WCLK. Upon the second
LOW-to-HIGH transition of WCLK, data are written into the Empty Offset
MSB Register. Upon the third LOW-to-HIGH transition of WCLK, data are
written into the Full Offset LSB Register. Upon the fourth LOW-to-HIGH
transition of WCLK, data are written into the Full Offset MSB Register. The
fifth transition of WCLK writes, once again, to the Empty Offset LSB Register.
See Figure 14,
Parallel Loading of Programmable Flag Registers for the
IDT72281
, for the timng diagramfor this mode.
For the IDT72291, programmng
PAE
and
PAF
proceeds as follows:
when
LD
and
WEN
are set LOW, data on the inputs Dn are written into the
Empty Offset LSB Register on the first LOW-to-HIGH transition of WCLK.
Upon the second LOW-to-HIGH transition of WCLK, data are written into the
Empty Offset Md-Byte Register. Upon the third LOW-to-HIGH transition of
WCLK, data are written into the Empty Offset MSB Register. Upon the fourth
LOW-to-HIGH transition of WCLK, data are written into the Full Offset LSB
Register. Upon the fifth LOW-to-HIGH transition of WCLK, data are written
into the Full Offset Md-Byte Register. Upon the sixth LOW-to-HIGH transi-
tion of WCLK, data are written into the Full Offset MSB Register. The sev-
enth transition of WCLK writes, once again, into the Empty Offset LSB Regis-
ter. See Figure 15,
Parallel Loading of Programmable Flag Registers for
the IDT72291
, for the timng diagramfor this mode.
The act of writing offsets in parallel employs a dedicated write offset
register pointer. The act of reading offsets employs a dedicated read offset
register pointer. The two pointers operate independently; however, a read
and a write should not be performed simultaneously to the offset registers. A
Master Reset initializes both pointers to the Empty Offset (LSB) register. A
Partial Reset has no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programmng sequence. In this case, the programmng of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing
LD
HIGH, write operations can be redirected
to the FIFO memory. When
LD
is set LOW again, and
WEN
is LOW, the
next offset register in sequence is written to. As an alternative to holding
WEN
LOW and toggling
LD
, parallel programmng can also be interrupted
by setting
LD
LOW and toggling
WEN
.
Note that the status of a partial flag (
PAE
or
PAF
) output is invalid during
the programmng process. Fromthe time parallel programmng has begun,
a partial flag output will not be valid until the appropriate offset word has
been written to the register(s) pertaining to that flag. Measuring fromthe
rising WCLK edge that achieves the above criteria;
PAF
will be valid after
two more rising WCLK edges plus t
PAF
,
PAE
will be valid after the next two
rising RCLK edges plus t
PAE
plus t
SKEW2
.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q
0
-
Q
n
pins when
LD
is set LOW and
REN
is set LOW. For the IDT72281, data
are read via Q
n
fromthe Empty Offset LSB Register on the first LOW-to-
HIGH transition of RCLK. Upon the second LOW-to-HIGH transition of RCLK,
data are read fromthe Empty Offset MSB Register. Upon the third LOW-to-
HIGH transition of RCLK, data are read fromthe Full Offset LSB Register.
Upon the fourth LOW-to-HIGH transition of RCLK, data are read fromthe
Full Offset MSB Register. The fifth transition of RCLK reads, once again,
fromthe Empty Offset LSB Register. See Figure 16,
Parallel Read of Pro-
grammable Flag Registers for the IDT72281
, for the timng diagramfor this
mode.
For the IDT72291, data is read via Q
n
fromthe Empty Offset LSB Regis-
ter on the first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-
HIGH transition of RCLK, data are read fromthe Empty Offset Md-Byte
Register. Upon the third LOW-to-HIGH transition of RCLK, data are read
fromthe Empty Offset MSB Register. Upon the fourth LOW-to-HIGH transi-
tion of RCLK, data are read fromthe Full Offset LSB Register. Upon the fifth
LOW-to-HIGH transition of RCLK, data are read fromthe Full Offset Md-
Byte Register. Upon the sixth LOW-to-HIGH transition of RCLK, data are
read fromthe Full Offset MSB Register. The seventh transition of RCLK
reads, once again, fromthe Empty Offset LSB Register. See Figure 17,
Parallel Read of Programmable Flag Registers for the IDT72291
, for the
timng diagramfor this mode.
It is permssible to interrupt the offset register read sequence with reads
or writes to the FIFO. The interruption is accomplished by deasserting
REN
,
LD
, or both together. When
REN
and
LD
are restored to a LOW
level, reading of the offset registers continues where it left off. It should be
noted, and care should be taken fromthe fact that when a parallel read of
the flag offsets is performed, the data word that was present on the output
lines Q
n
will be overwritten.
Parallel reading of the offset registers is always permtted regardless of
which timng mode (IDT Standard or FWFT modes) has been selected.
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參數(shù)描述
IDT72281L10PF 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72281L10PF8 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72281L10PFG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP
IDT72281L10PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP
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