參數(shù)資料
型號(hào)： IDT72281L
廠商： Integrated Device Technology, Inc.
英文描述： CMOS SuperSync FIFO
中文描述： 先進(jìn)先出的CMOS SuperSync
文件頁(yè)數(shù)： 3/26頁(yè)
文件大?。?/td> 277K
代理商： IDT72281L
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
DESCRIPTION (CONTINUED)
Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO
DATA OUT (Q
0
- Q
n
)
DATA IN (D
0
- D
n
)
MASTER RESET (
MRS
)
READ CLOCK (RCLK)
READ ENABLE (
REN
)
OUTPUT ENABLE (
OE
)
EMPTY FLAG/OUTPUT READY (
EF
/
OR
)
PROGRAMMABLE ALMOST-EMPTY (
PAE
)
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN
)
LOAD (
LD
)
FULL FLAG/INPUT READY (
FF
/
IR
)
PROGRAMMABLE ALMOST-FULL (
PAF
)
IDT
72281
72291
PARTIAL RESET (
PRS
)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (
RT
)
4675 drw 03
HALF-FULL FLAG (
HF
)
SERIAL ENABLE(
SEN
)
FWFT mode.
HF
,
PAE
and
PAF
are always available for use, irrespective of
timng mode.
PAE
and
PAF
can be programmed independently to switch at any point in
memory. (See Table I and Table II.) Programmable offsets determne the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, so that
PAE
can be set to switch at 127
or 1,023 locations fromthe empty boundary and the
PAF
threshold can be set
at 127 or 1,023 locations fromthe full boundary. These choices are made with
the
LD
pin during Master Reset.
For serial programmng,
SEN
together with
LD
on each rising edge of WCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programmng,
WEN
together with
LD
on each rising edge of WCLK, are used
to load the offset registers via D
n
.
REN
together with
LD
on each rising edge
of RCLK can be used to read the offsets in parallel fromQn regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (
MRS
) the following events occur: The read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The
LD
pin selects either a partial flag default
setting of 127 with parallel programmng or a partial flag default setting of 1,023
with serial programmng. The flags are updated according to the timng mode
and default offsets selected.
The Partial Reset (
PRS
) also sets the read and write pointers to the first
location of the memory. However, the timng mode, partial flag programmng
method, and default or programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the timng mode and
offsets in effect.
PRS
is useful for resetting a device in md-operation, when
reprogrammng partial flags would be undesirable.
The Retransmt function allows data to be reread fromthe FIFO more than
once. A LOW on the
RT
input during a rising RCLK edge initiates a retransmt
operation by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performng an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is mnimzed. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72281/72291 are fabricated using IDT’s high speed submcron
CMOS technology.
相關(guān)PDF資料
PDF描述
IDT72281L10PF CMOS SuperSync FIFO
IDT72281L10PFI CMOS SuperSync FIFO
IDT72281L10TF CMOS SuperSync FIFO
IDT723612L15PF BiCMOS SyncBiFIFOO 64 x 36 x 2
IDT723612L15PQF BiCMOS SyncBiFIFOO 64 x 36 x 2
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72281L10PF 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72281L10PF8 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72281L10PFG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP
IDT72281L10PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP
IDT72281L10TF 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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