- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377415 > IDT72281L (Integrated Device Technology, Inc.) CMOS SuperSync FIFO PDF資料下載
參數(shù)資料
| 型號： | IDT72281L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SuperSync FIFO |
| 中文描述： | 先進先出的CMOS SuperSync |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 277K |
| 代理商： | IDT72281L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
12
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D
0
- D
8
)
Data inputs for 9-bit wide data.
CONTROLS:
MASTER RESET
(
MRS
)
A Master Reset is accomplished whenever the
MRS
input is taken to a
LOW state. This operation sets the internal read and write pointers to the first
location of the RAMarray.
PAE
will go LOW,
PAF
will go HIGH, and
HF
will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with
EF
and
FF
are selected.
EF
will go LOW and
FF
will go HIGH. If
FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR
and
OR
, are selected.
OR
will go HIGH and
IR
will go LOW.
If
LD
is LOW during Master Reset, then
PAE
is assigned a threshold 127
words fromthe empty boundary and
PAF
is assigned a threshold 127
words fromthe full boundary; 127 words corresponds to an offset value of
07FH. Following Master Reset, parallel loading of the offsets is permtted,
but not serial loading.
If
LD
is HIGH during Master Reset, then
PAE
is assigned a threshold
1,023 words fromthe empty boundary and
PAF
is assigned a threshold
1,023 words fromthe full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permtted, but not parallel loading.
Parallel reading of the registers is always permtted. (See section de-
scribing the
LD
pin for further details.)
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place.
MRS
is asynchronous.
See Figure 5,
Master Reset Timng
, for the relevant timng diagram
PARTIAL RESET
(
PRS
)
A Partial Reset is accomplished whenever the
PRS
input is taken to a
LOW state. As in the case of the Master Reset, the internal read and write
pointers are set to the first location of the RAMarray,
PAE
goes LOW,
PAF
goes HIGH, and
HF
goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT
Standard mode is active, then
FF
will go HIGH and
EF
will go LOW. If the
First Word Fall Through mode is active, then
OR
will go HIGH, and
IR
will
go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programmng method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes.
PRS
is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogrammng partial flag offset settings may not be con-
venient.
See Figure 6,
Partial Reset Timng
, for the relevant timng diagram
RETRANSMIT
(
RT
)
The Retransmt operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmt,
which consists of reading out the memory contents, starting at the beginning
of the memory.
Retransmt setup is initiated by holding
RT
LOW during a rising RCLK
edge.
REN
and
WEN
must be HIGH before bringing
RT
LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmt setup by setting
EF
LOW. The change in level will only be
noticeable if
EF
was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAMarray.
When
EF
goes HIGH, Retransmt setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following Re-
transmt setup requires a LOW on
REN
to enable the rising edge of RCLK.
See Figure 11,
Retransmt Timng (IDT Standard Mode)
, for the relevant
timng diagram
If FWFT mode is selected, the FIFO will mark the beginning of the Re-
transmt setup by setting
OR
HIGH. During this period, the internal read
pointer is set to the first location of the RAMarray.
When
OR
goes LOW, Retransmt setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on
REN
is neces-
sary. Reading all subsequent words requires a LOW on
REN
to enable the
rising edge of RCLK. See Figure 12,
Retransmt Timng (FWFT Mode)
, for
the relevant timng diagram
FIRST WORD FALL THROUGH/SERIAL IN
(
FWFT/SI
)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determnes whether the device will operate in IDT Standard mode
or First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag
(
EF
) to indicate whether
or not there are any words present in the FIFO memory. It also uses the
Full Flag function (
FF
) to indicate whether or not the FIFO memory has any
free space for writing. In IDT Standard mode, every word read fromthe
FIFO, including the first, must be requested using the Read Enable (
REN
)
and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (
OR
) to indicate whether or not
there is valid data at the data outputs (Q
n
). It also uses Input Ready (
IR
) to
indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to Q
n
after three RCLK rising edges,
REN
= LOW is not necessary. Subsequent
words must be accessed using the Read Enable (
REN
) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading
PAE
and
PAF
offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programmng using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
WRITE CLOCK (WCLK
)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permssible to stop the WCLK. Note that while WCLK is idle, the
FF
/
IR
,
PAF
and
HF
flags will not be updated. (Note that WCLK is only
capable of updating
HF
flag to LOW.) The Write and Read Clocks can
either be independent or coincident.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72281L10PF | CMOS SuperSync FIFO |
| IDT72281L10PFI | CMOS SuperSync FIFO |
| IDT72281L10TF | CMOS SuperSync FIFO |
| IDT723612L15PF | BiCMOS SyncBiFIFOO 64 x 36 x 2 |
| IDT723612L15PQF | BiCMOS SyncBiFIFOO 64 x 36 x 2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72281L10PF | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72281L10PF8 | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72281L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP |
| IDT72281L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP |
| IDT72281L10TF | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。