參數(shù)資料
型號(hào)： IDT72281L
廠商： Integrated Device Technology, Inc.
英文描述： CMOS SuperSync FIFO
中文描述： 先進(jìn)先出的CMOS SuperSync
文件頁(yè)數(shù)： 23/26頁(yè)
文件大?。?/td> 277K
代理商： IDT72281L
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
NOTES:
1. m=
PAF
offset.
2. D = maximumFIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
In FWFT mode: D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
3. t
SKEW2
is the mnimumtime between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF
will go HIGH (after one WCLK cycle plus t
PAF
). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then the
PAF
deassertion time may be delayed one extra WCLK cycle.
4.
PAF
is asserted and updated on the rising edge of WCLK only.
Figure 18. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAF
RCLK
(3)
REN
4675 drw 21
t
ENS
t
ENH
t
ENS
D - (m+1) words in FIFO
(2)
t
SKEW2
1
2
1
2
D-(m+1) words
in FIFO
t
PAF
D - m words in FIFO
(2)
t
PAF
NOTES:
1. n =
PAE
offset.
2. For IDT Standard mode.
3. For FWFT mode.
4. t
SKEW2
is the mnimumtime between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE
will go HIGH (after one RCLK cycle plus t
PAE
). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then the
PAE
deassertion may be delayed one extra RCLK cycle.
5.
PAE
is asserted and updated on the rising edge of WCLK only.
Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
t
ENS
t
PAE
t
SKEW2
t
PAE
1
2
1
2
(4)
REN
4675 drw 22
t
ENS
t
ENH
n+1 words in FIFO
(2),
n+2 words in FIFO
(3)
n words in FIFO
(2),
n+1 words in FIFO
(3)
n words in FIFO
(2),
n+1 words in FIFO
(3)
WCLK
t
ENS
t
ENH
WEN
HF
t
ENS
RCLK
REN
4675 drw 23
D/2 words in FIFO
(1)
,
[
+ 1
words in FIFO
(2)
D-1
D/2 + 1 words in FIFO
(1)
,
[
+ 2
words in FIFO
(2)
D-1
D/2 words in FIFO
(1)
,
[
+ 1
words in FIFO
(2)
D-1
t
CLKH
t
CLKL
t
HF
t
HF
Figure 19. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. For IDT Standard mode: D = maximumFIFO depth. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
2. For FWFT mode: D = maximumFIFO depth. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
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