- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377415 > IDT72281L (Integrated Device Technology, Inc.) CMOS SuperSync FIFO PDF資料下載
參數(shù)資料
| 型號： | IDT72281L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SuperSync FIFO |
| 中文描述： | 先進(jìn)先出的CMOS SuperSync |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 277K |
| 代理商： | IDT72281L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
14
valid on the outputs.
OR
stays LOW after the RCLK LOW to HIGH transition
that shifts the last word fromthe FIFO memory to the outputs.
OR
goes
HIGH only with a true read (RCLK with
REN
= LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until
OR
goes LOW again. See Figure 10,
Read Timng
(FWFT Mode)
, for the relevant timng information.
EF
/
OR
is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF
is a double register-buffered output. In FWFT
mode,
OR
is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF
)
The Programmable Almost-Full flag (
PAF
) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS
),
PAF
will go LOW after (D – m words are
written to the FIFO.
The
PAF
will go LOW after (65,536–m writes for the
IDT72281 and (131,072–m writes for the IDT72291. The offset “m” is the
full offset value. The default setting for this value is stated in the footnote of
Table 1.
In FWFT mode, the
PAF
will go LOW after (65,53–m writes for the
IDT72281 and (131,073–m writes for the IDT72291, where mis the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
See Figure 18,
Programmable Almost-Full Flag Timng (IDT Standard
and FWFT Mode)
, for the relevant timng information.
PAF
is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE
)
The Programmable Almost-Empty flag (
PAE
) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode,
PAE
will go
LOW when there are n words or less in the FIFO. The offset “n” is the
empty offset value. The default setting for this value is stated in the footnote
of Table 1.
In FWFT mode, the
PAE
will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
See Figure 19,
Programmable Almost-Empty Flag Timng (IDT Stan-
dard and FWFT Mode)
, for the relevant timng information.
PAE
is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF
)
This output indicates a half-full FIFO. The rising WCLK edge that fills the
FIFO beyond half-full sets
HF
LOW. The flag remains LOW until the differ-
ence between the write and read pointers becomes less than or equal to
half of the total depth of the device; the rising RCLK edge that accomplishes
this condition sets
HF
HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS
or
PRS)
,
HF
will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536
for the IDT72281 and 131,072 for the IDT72291.
In FWFT mode, if no reads are performed after reset (
MRS
or
PRS
),
HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for the
IDT72281 and 131,073 for the IDT72291.
See Figure 20,
Half-Full Flag Timng (IDT Standard and FWFT Modes)
,
for the relevant timng information. Because
HF
is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
0
-Q
8
)
(Q
0
- Q
8
) are data outputs for 9-bit wide data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72281L10PF | CMOS SuperSync FIFO |
| IDT72281L10PFI | CMOS SuperSync FIFO |
| IDT72281L10TF | CMOS SuperSync FIFO |
| IDT723612L15PF | BiCMOS SyncBiFIFOO 64 x 36 x 2 |
| IDT723612L15PQF | BiCMOS SyncBiFIFOO 64 x 36 x 2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72281L10PF | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72281L10PF8 | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72281L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP |
| IDT72281L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP |
| IDT72281L10TF | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。