參數(shù)資料
型號(hào): IDT72281L
廠商: Integrated Device Technology, Inc.
英文描述: CMOS SuperSync FIFO
中文描述: 先進(jìn)先出的CMOS SuperSync
文件頁(yè)數(shù): 17/26頁(yè)
文件大?。?/td> 277K
代理商: IDT72281L
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
NOTES:
1. t
SKEW3
is the mnimumtime between a rising WCLK edge and a rising RCLK edge to guarantee that
EF
will go HIGH (after one RCLK cycle plus t
REF
). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW3
, then
EF
deassertion may be delayed one extra RCLK cycle.
2.
LD
= HIGH.
NOTES:
1. t
SKEW1
is the mnimumtime between a rising RCLK edge and a rising WCLK edge to guarantee that
FF
will go high (after one WCLK cycle pus t
WFF
). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than t
SKEW1
, then the
FF
deassertion may be delayed one extra WCLK cycle.
2.
LD
= HIGH,
OE
= LOW,
EF
= HIGH.
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
D
0
- D
n
WEN
RCLK
REN
t
ENH
t
ENH
Q
0
- Q
n
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
t
SKEW1
(1)
4675 drw 10
WCLK
NO WRITE
1
2
1
2
t
DS
NO WRITE
t
WFF
t
WFF
t
WFF
t
ENS
t
ENS
t
SKEW1
(1)
t
DS
D
X
t
DH
D
X
+1
t
WFF
t
DH
t
CLK
t
CLKL
t
CLKH
t
A
t
A
RCLK
REN
4675 drw 11
EF
t
ENH
t
REF
t
A
t
OLZ
t
OE
Q
0
- Q
n
OE
WCLK
(1)
t
SKEW3
WEN
D
0
- D
n
t
ENS
t
ENS
t
ENH
t
DS
t
DHS
D
0
1
2
t
OLZ
LAST WORD
D
0
D
1
D
1
t
ENS
t
ENH
t
DS
t
DH
t
OHZ
LAST WORD
t
ENH
t
ENS
t
A
t
A
t
ENS
t
ENH
t
CLK
t
CLKH
t
CLKL
t
REF
t
REF
NO OPERATION
NO OPERATION
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