- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377415 > IDT72281L (Integrated Device Technology, Inc.) CMOS SuperSync FIFO PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT72281L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SuperSync FIFO |
| 中文描述： | 先進(jìn)先出的CMOS SuperSync |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 277K |
| 代理商： | IDT72281L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72281 can easily be adapted to applications requiring depths greater
than 65,536 and 131,072 for the IDT72291 with a 9-bit bus width. In FWFT
mode, the FIFOs can be connected in series (the data outputs of one FIFO
connected to the data inputs of the next) with no external logic necessary. The
resulting configuration provides a total depth equivalent to the sumof the depths
associated with each single FIFO. Figure 24 shows a depth expansion using
two IDT72281/72291 devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass fromone FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
OR
of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sumof the delays
for each individual FIFO:
(N – 1)*4*transfer clock) + 3*T
RCLK
where N is the number of FIFOs in the expansion and T
RCLK
is the RCLK period.
Note that extra cycles should be added for the possibility that the t
SKEW3
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the
OR
flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading froma full depth expansion
configuration will "bubble up" fromthe last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's
IR
line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for
IR
of the first
FIFO in the chain to go LOW after a word has been read fromthe last FIFO is
the sumof the delays for each individual FIFO:
(N – 1)*3*transfer clock) + 2 T
WCLK
where N is the number of FIFOs in the expansion and T
WCLK
is the WCLK
period. Note that extra cycles should be added for the possibility that the t
SKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the
IR
flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
Figure 22. Block Diagram of 131,072 x 9 and 262,144 x 9 Depth Expansion
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
IDT
72281
72291
TRANSFER CLOCK
4675 drw 25
n
n
n
FWFT/SI
FWFT/SI
FWFT/SI
IDT
72281
72291
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72281L10PF | CMOS SuperSync FIFO |
| IDT72281L10PFI | CMOS SuperSync FIFO |
| IDT72281L10TF | CMOS SuperSync FIFO |
| IDT723612L15PF | BiCMOS SyncBiFIFOO 64 x 36 x 2 |
| IDT723612L15PQF | BiCMOS SyncBiFIFOO 64 x 36 x 2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72281L10PF | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72281L10PF8 | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72281L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP |
| IDT72281L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP |
| IDT72281L10TF | 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。