- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10742 > ICS1893AFLF (IDT, Integrated Device Technology Inc)PHYCEIVER LOW PWR 3.3V 48-SSOP PDF資料下載
參數(shù)資料
| 型號： | ICS1893AFLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 94/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 1893AFLF 800-2353-5 ICS1893AFLF-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁當(dāng)前第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁
ICS1893AF, Rev D 10/26/04
October, 2004
60
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.2.2
Loopback Enable (bit 0.14)
This bit controls the Loopback mode for the ICS1893AF. Setting this bit to logic:
Zero disables the Loopback mode.
One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver,
and the collision detection circuitry. (The STA can override the ICS1893AF from disabling the collision
detection circuitry in Loopback mode by writing logic one to bit 0.7.) When the ICS1893AF is in Loopback
mode, the data presented at the MAC/repeater transmit interface is internally looped back to the
MAC/repeater receive interface. The delay from the assertion of Transmit Data Enable (TXEN) to the
assertion of Receive Data valid (RXDV) is less than 512 bit times.
8.2.3
Data Rate Select (bit 0.13)
This bit provides a means of controlling the ICS1893AF data rate. Its operation depends on the state of
several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12).
When the ICS1893AF is configured for:
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893AF isolates this bit 0.13 and uses the
10/100SEL input pin to establish the data rate for the ICS1893AF. In this Hardware mode:
– Bit 0.13 is undefined.
– The ICS1893AF provides a Data Rate Status bit (in the QuickPoll Detailed Status Register, bit 17.15),
which always shows the setting of an active link.
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.13 depends on the
Auto-Negotiation Enable bit 0.12. When the Auto-Negotiation sublayer is:
– Enabled, the ICS1893AF isolates bit 0.13 and relies on the results of the auto-negotiation process to
establish the data rate.
– Disabled, bit 0.13 determines the data rate. In this case, setting bit 0.13 to logic:
Zero selects 10-Mbps ICS1893AF operations.
One selects 100-Mbps ICS1893AF operations.
8.2.4
Auto-Negotiation Enable (bit 0.12)
This bit provides a means of controlling the ICS1893AF Auto-Negotiation sublayer. Its operation depends
on the HW/SW input pin.
When the ICS1893AF is configured for:
Hardware mode, (that is, the HW/SW pin is logic zero), the ICS1893AF isolates bit 0.12 and uses the
ANSEL (Auto-Negotiation Select) input pin to determine whether to enable the Auto-Negotiation
sublayer.
Note:
In Hardware mode, bit 0.12 is undefined.
Software mode, (that is, the HW/SW pin is logic one), bit 0.12 determines whether to enable the
Auto-Negotiation sublayer. When bit 0.12 is logic:
– Zero:
The ICS1893AF disables the Auto-Negotiation sublayer.
The ICS1893AF bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data
rate and the duplex mode.
– One:
The ICS1893AF enables the Auto-Negotiation sublayer.
The ICS1893AF isolates bit 0.13 and bit 0.8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-JNN-MY-F2 | CONVERTER MOD DC/DC 18.5V 50W |
| ADCMP606BKSZ-R2 | IC COMP TTL/CMOS 1CHAN SC70-6 |
| VE-JNM-MY-F4 | CONVERTER MOD DC/DC 10V 50W |
| MAX976EUA+ | IC COMPARATOR DUAL 8-UMAX |
| ISL98003INZ-110 | IC AFE 3CH 8BIT 110MHZ 80EPTQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。