參數(shù)資料
型號： ICS1893AFLF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 92/136頁
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應商設備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893AFLF
800-2353-5
ICS1893AFLF-ND
Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
59
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.2
Register 0: Control Register
Table 8-5 lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes
of the ICS1893AF.
The Control Register is accessible through the MII Management Interface.
Its operation is independent of the MAC/Repeater Interface configuration.
It is fully compliant with the ISO/IEC Control Register definition.
Note:
For an explanation of acronyms used in Table 8-5, see Chapter 1, “Abbreviations and Acronyms”.
Whenever the PHY address of Table 8-16:
Is equal to 00000 (binary), the Isolate bit 0.10 is logic one.
Is not equal to 00000, the Isolate bit 0.10 is logic zero.
As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
8.2.1
Reset (bit 0.15)
This bit controls the software reset function. Setting this bit to logic one initiates an ICS1893AF software
reset during which all Management Registers are set to their default values and all internal state machines
are set to their idle state. For a detailed description of the software reset process, see Section 5.1.2.3,
During reset, the ICS1893AF leaves bit 0.15 set to logic one and isolates all STA management register
accesses. However, the reset process is not complete until bit 0.15 (a Self-Clearing bit), is set to logic zero,
which indicates the reset process is terminated.
Table 8-5.
Control Register (Register 0 [0x00]
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
0.15
Reset
No effect
ICS1893AF enters Reset
mode
R/W
SC
0
3
0.14
Loopback enable
Disable Loopback mode
Enable Loopback mode
R/W
–
0
0.13
Data rate select
10 Mbps operation
100 Mbps operation
R/W
–
1
0.12
Auto-Negotiation enable
Disable Auto-Negotiation
Enable Auto-Negotiation
R/W
–
1
0.11
Low-power mode
Normal power mode
Low-power mode
R/W
–
0
0/4
0.10
Isolate
No effect
Isolate ICS1893AF from
MII
R/W
–
0/1
0.9
Auto-Negotiation restart
No effect
Restart Auto-Negotiation
R/W
SC
0
0.8
Duplex mode
Half-duplex operation
Full-duplex operation
R/W
–
0
0.7
Collision test
No effect
Enable collision test
R/W
–
0
0.6
IEEE reserved
Always 0
N/A
RO
–
0
0.5
IEEE reserved
Always 0
N/A
RO
–
0
0.4
IEEE reserved
Always 0
N/A
RO
–
0
0.3
IEEE reserved
Always 0
N/A
RO
–
0
0.2
IEEE reserved
Always 0
N/A
RO
–
0
0.1
IEEE reserved
Always 0
N/A
RO
–
0
0.0
IEEE reserved
Always 0
N/A
RO
–
0
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ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
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