參數(shù)資料
型號(hào)： ICS1893AFLF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 130/136頁(yè)
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893AFLF
800-2353-5
ICS1893AFLF-ND
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Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
93
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.13
Register 18: 10Base-T Operations Register
The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893AF
activity while the ICS1893AF is operating in 10Base-T mode.
Note:
1.
For an explanation of acronyms used in Table 8-20, see Chapter 1, “Abbreviations and Acronyms”.
2.
During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
8.13.1
Remote Jabber Detect (bit 18.15)
The Remote Jabber Detect bit is provided to indicate that an ICS1893AF port has detected a Jabber
Condition on its receive path. This bit is reset to logic zero on a read of the 10Base-T operations register.
When this bit is logic:
Zero, it indicates a Jabber Condition has not occurred on the port’s receive path since either the last read
of this register or the last reset of the associated port.
One, it indicates a Jabber Condition has occurred on the port’s receive path since either the last read of
this register or the last reset of the associated port.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note:
This bit is provided for information purposes only (that is, no actions are taken by the port). The
ISO/IEC specification defines the Jabber Condition in terms of a port’s transmit path. To set this bit,
an ICS1893AF port monitors its receive path and applies the ISO/IEC Jabber criteria to its receive
path.
Table 8-20.
10Base-T Operations Register (register 18 [0x12])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
18.15
Remote Jabber
Detect
No Remote Jabber
Condition detected
Remote Jabber Condition
Detected
RO
LH
0
–
18.14
Polarity reversed
Normal polarity
Polarity reversed
RO
LH
0
18.13
ICS reserved
Read unspecified
RW/0
–
18.12
ICS reserved
Read unspecified
RW/0
–
18.11
ICS reserved
Read unspecified
RW/0
–
18.10
ICS reserved
Read unspecified
RW/0
–
18.9
ICS reserved
Read unspecified
RW/0
–
18.8
ICS reserved
Read unspecified
RW/0
–
18.7
ICS reserved
Read unspecified
RW/0
–
18.6
ICS reserved
Read unspecified
RW/0
–
18.5
Jabber inhibit
Normal Jabber behavior
Jabber Check disabled
RW
–
0
18.4
ICS reserved
Read unspecified
RW/1
–
1
18.3
Auto polarity inhibit
Polarity automatically
corrected
Polarity not automatically
corrected
RW
–
0
18.2
SQE test inhibit
Normal SQE test behavior
SQE test disabled
RW
–
0
18.1
Link Loss inhibit
Normal Link Loss behavior Link Always = Link Pass
RW
–
0
18.0
Squelch inhibit
Normal squelch behavior
No squelch
RW
–
0
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參數(shù)描述
ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AG 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGI 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGILF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
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