參數(shù)資料
型號： ICS1893AFLF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 101/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應商設(shè)備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893AFLF
800-2353-5
ICS1893AFLF-ND
Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
67
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.3.11
Link Status (bit 1.2)
The purpose of this bit 1.2 (which is also accessible through the QuickPoll Detailed Status Register, bit
17.0) is to determine if an established link is dropped, even momentarily. To indicate a link that is:
Valid, the ICS1893AF sets bit 1.2 to logic one.
Invalid, the ICS1893AF clears bit 1.2 to logic zero.
This bit is a latching low (LL) bit that the Link Monitor function controls. (For more information on latching
Bits”.) The Link Monitor function continually observes the data received by either its 10Base-T or
100Base-TX Twisted-Pair Receivers to determine the link status and stores the results in the Link Status
bit.
The criterion the Link Monitor uses to determine if a link is valid or invalid depends on the following:
Type of link
Present link state (valid or invalid)
Presence of any link errors
Auto-negotiation process
For more information on the Link Monitor Function (relative to the Link Status bit), see Section 7.5.5,
8.3.12
Jabber Detect (bit 1.1)
The purpose of this bit is to allow an STA to determine if the ICS1893AF detects a Jabber condition as
defined in the ISO/IEC specification.The ICS1893AF Jabber Detection function is controlled by the Jabber
Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893AF
Jabber Detection function must be enabled. When bit 18.5 is logic:
Zero, the ICS1893AF disables Jabber Detection and sets the Jabber Detect bit to logic zero.
One, the ICS1893AF enables Jabber Detection and sets the Jabber Detect bit to logic one upon
detection of a Jabber condition. When no Jabber condition is detected, the Jabber Detect bit is not
altered.
Note:
1.
The Jabber Detect bit is accessible through both the Status register (as bit 1.1) and the QuickPoll
Detailed Status Register (as bit 17.2). A read of either register clears the Jabber Detect bit.
2.
The Jabber Detect bit is a latching high (LH) bit. (For more information on latching high and latching low
8.3.13
Extended Capability (bit 1.0)
The STA reads bit 1.0 to determine if the ICS1893AF has an extended register set. In the ICS1893AF this
bit is always logic one, indicating that it has extended registers.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AG 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGI 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGILF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
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