參數(shù)資料
型號(hào): ICS1893AFLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 39/136頁
文件大?。?/td> 0K
描述: PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝: 30
系列: PHYceiver™
類型: PHY 收發(fā)器
規(guī)程: MII
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 管件
其它名稱: 1893AFLF
800-2353-5
ICS1893AFLF-ND
Chapter 10
DC and AC Operating Conditions
ICS1893AF, Rev. D 10/26/04
October, 2004
133
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
10.5.20
Auto-Negotiation Fast Link Pulse Timing
Table 10-27 lists the significant time periods for the ICS1893AF Auto-Negotiation Fast Link Pulse. The time
periods consist of timings of signals on the following pins:
TP_TXP
TP_TXN
Figure 10-21 shows the timing diagram for one pair of these differential signals, for example TP_TXP minus
TP_TXN.
Figure 10-21.
Auto-Negotiation Fast Link Pulse Timing Diagram
Table 10-27.
Auto-Negotiation Fast Link Pulse Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
Clock/Data Pulse Width
90
ns
t2
Clock Pulse-to-Data Pulse Timing
55
60
70
s
t3
Clock Pulse-to-Clock Pulse Timing
110
125
140
s
t4
Fast Link Pulse Burst Width
5
ms
t5
Fast Link Pulse Burst to Fast Link Pulse Burst
10
15
25
ms
t6
Number of Clock/Data Pulses in a Burst
15
20
30
pulses
Clock
Pulse
Clock
Pulse
Data
Pulse
t1
t3
t2
t4
t5
t1
FLP Burst
Differential
Twisted Pair
Transmit Signal
Differential
Twisted Pair
Transmit Signal
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