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參數(shù)資料
| 型號： | ICS1893AFLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 107/136頁 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標準包裝： | 30 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 1893AFLF 800-2353-5 ICS1893AFLF-ND |
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ICS1893AF, Rev D 10/26/04
October, 2004
72
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.6
Register 4: Auto-Negotiation Register
Table 8-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the
ICS1893AF capabilities that it wants to advertise to its remote link partner. During the auto-negotiation
process, the ICS1893AF advertises (that is, exchanges) capability data with its remote link partner by using
a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged
between PHYs when the ICS1893AF has its Auto-Negotiation sublayer enabled. The value of the Link
Control Word is established based on the value of the bits in this register.
Note:
For an explanation of acronyms used in Table 8-5, see Chapter 1, “Abbreviations and Acronyms”.
As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
8.6.1
Next Page (bit 4.15)
This bit indicates whether the ICS1893AF uses the Next Page Mode functions during the auto-negotiation
process. If bit 4.15 is logic:
Zero, then the ICS1893AF indicates to its remote link partner that these features are disabled. (Although
the default value of this bit is logic zero, the ICS1893AF does support the Next Page function.)
One, then the ICS1893AF advertises to its remote link partner that this feature is enabled.
8.6.2
IEEE Reserved Bit (bit 4.14)
The ISO/IEC specification reserves this bit for future use. However, the ISO/IEC Standard also defines bit
4.14 as the Acknowledge bit.
Table 8-11.
Auto-Negotiation Advertisement Register (register 4 [0x04])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
4.15
Next Page
Next page not supported
Next page supported
R/W
–
0
4.14
IEEE reserved
Always 0
N/A
CW
–
0
4.13
Remote fault
Locally, no faults detected
Local fault detected
R/W
–
0
4.12
IEEE reserved
Always 0
N/A
CW
–
0
4.11
IEEE reserved
Always 0
N/A
CW
–
0
1
4.10
IEEE reserved
Always 0
N/A
CW
–
0
4.9
100Base-T4
Always 0. (Not supported.)
N/A
CW
–
0
4.8
100Base-TX, full duplex
Do not advertise ability
Advertise ability
R/W
–
1
4.7
100Base-TX, half duplex Do not advertise ability
Advertise ability
R/W
–
1
E
4.6
10Base-T, full duplex
Do not advertise ability
Advertise ability
R/W
–
1
4.5
10Base-T half duplex
Do not advertise ability
Advertise ability
R/W
–
1
4.4
Selector Field bit S4
IEEE 802.3-specified default N/A
CW
–
0
4.3
Selector Field bit S3
IEEE 802.3-specified default N/A
CW
–
0
1
4.2
Selector Field bit S2
IEEE 802.3-specified default N/A
CW
–
0
4.1
Selector Field bit S1
IEEE 802.3-specified default N/A
CW
–
0
4.0
Selector Field bit S0
N/A
IEEE 802.3-specified
default
CW
–
1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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