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參數(shù)資料
| 型號(hào)： | ICS1893AFLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 134/136頁(yè) |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 1893AFLF 800-2353-5 ICS1893AFLF-ND |
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Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
97
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.14.1
Node/Repeater Configuration (bit 19.15)
The Node/Repeater Configuration bit indicates the NOD/MODE.
In Node mode:
– The SQE Test default setting is enabled.
– The Carrier Sense signal (CRS) is asserted in response to either transmit or receive activity.
8.14.2
Hardware/Software Priority Status (bit 19.14)
The Hardware/Software Priority Status bit indicates the SW mode.
The (MDIO) register bits control the ICS1893AF configuration.
8.14.3
Remote Fault (bit 19.13)
The ISO/IEC specification defines bit 5.13 as the Remote Fault bit, and bit 19.13 is functionally identical to
bit 5.13. The Remote Fault bit is set based on the Link Control Word received from the remote link partner.
When this bit is a logic:
Zero, it indicates the remote link partner does not detect a Link Fault.
One, it indicates to an STA that the remote link partner detects a Link Fault.
8.14.4
ICS Reserved (bits 19.12:8)
See Section 8.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.
8.14.5
Twisted Pair Tri-State Enable, TPTRI (bit 19.7)
The ICS1893AF provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN
signals to a high-impedance state. When this bit is set to logic:
Zero, the Twisted Pair Interface is operational.
One, the Twisted Pair Interface is tri-stated.
8.14.6
ICS Reserved (bits 19.6:1)
See Section 8.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.
8.14.7
Automatic 100Base-TX Power-Down (bit 19.0)
The Automatic 100Base-TX Power Down bit provides an STA with the means of enabling the ICS1893AF
to automatically shut down 100Base-TX support functions when 10Base-T operations are being used.
When this bit is set to logic:
Zero, the 100Base-TX Transceiver does not power down automatically in 100Base-TX mode.
One, and the ICS1893AF is operating in 10Base-T mode, the 100Base-TX Transceiver automatically
turns off to reduce the overall power consumption of the ICS1893AF.
Note:
There are other means of powering down the 100Base-TX Transceiver (for example, when the
entire device is isolated using bit 0:10).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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