參數(shù)資料
型號： ICS1893AFLF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 123/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應商設備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893AFLF
800-2353-5
ICS1893AFLF-ND
Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
87
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.12
Register 17: Quick Poll Detailed Status Register
Table 8-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only
register used to provide an STA with detailed status of the ICS1893AF operations. During reset, it is
initialized to pre-defined default values.
Note:
1.
For an explanation of acronyms used in Table 8-18, see Chapter 1, “Abbreviations and Acronyms”.
2.
Most of this register’s bits are latching high or latching low, which allows the ICS1893AF to capture and
save the occurrence of an event for an STA to read. (For more information on latching high and latching
3.
Although some of these status bits are redundant with other management registers, the ICS1893AF
provides this group of bits to minimize the number of Serial Management Cycles required to collect the
status data.
Table 8-18.
Quick Poll Detailed Status Register (register 17 [0x11])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
17.15
Data rate
10 Mbps
100 Mbps
RO
–
17.14
Duplex
Half duplex
Full duplex
RO
–
17.13
Auto-Negotiation
Progress Monitor Bit 2
Reference Decode Table
RO
LMX
0
17.12
Auto-Negotiation
Progress Monitor Bit 1
Reference Decode Table
RO
LMX
0
17.11
Auto-Negotiation
Progress Monitor Bit 0
Reference Decode Table
RO
LMX
0
17.10
100Base-TX signal
lost
Valid signal
Signal lost
RO
LH
0
17.9
100BasePLL Lock
Error
PLL locked
PLL failed to lock
RO
LH
0
17.8
False Carrier detect
Normal Carrier or Idle
False Carrier
RO
LH
0
17.7
Invalid symbol
detected
Valid symbols observed
Invalid symbol received
RO
LH
0
17.6
Halt Symbol detected
No Halt Symbol received
Halt Symbol received
RO
LH
0
17.5
Premature End
detected
Normal data stream
Stream contained two
IDLE symbols
RO
LH
0
17.4
Auto-Negotiation
complete
Auto-Negotiation in
process
Auto-Negotiation
complete
RO
–
0
17.3
100Base-TX signal
detect
Signal present
No signal present
RO
–
0
17.2
Jabber detect
No jabber detected
Jabber detected
RO
LH
0
17.1
Remote fault
No remote fault detected
Remote fault detected
RO
LH
0
17.0
Link Status
Link is not valid
Link is valid
RO
LL
0
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參數(shù)描述
ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AG 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGI 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGILF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
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