參數(shù)資料
型號: ICS1893AFLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 133/136頁
文件大小: 0K
描述: PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝: 30
系列: PHYceiver™
類型: PHY 收發(fā)器
規(guī)程: MII
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 管件
其它名稱: 1893AFLF
800-2353-5
ICS1893AFLF-ND
ICS1893AF, Rev D 10/26/04
October, 2004
96
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.14
Register 19: Extended Control Register 2
The Extended Control Register provides more refined control of the internal ICS1893AF operations.
Note:
1.
For an explanation of acronyms used in Table 8-20, see Chapter 1, “Abbreviations and Acronyms”.
2.
During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
The default is the state of this pin at reset.
Table 8-21.
Extended Control Register (register [0x13])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
19.15
Node/Repeater Mode
Node mode
Repeater mode
RO
0
4
19.14
Hardware/Software
Mode
Hardware mode
Software mode
RO
1
19.13
Remote Fault
No faults detected
Remote fault
detected
RO
0
19.12
ICS reserved
Read unspecified
RW
0
19.11
ICS reserved
Read unspecified
RW
0
19.10
ICS reserved
Read unspecified
RO
0
19.9
ICS reserved
Read unspecified
RW
0
19.8
ICS reserved
Read unspecified
RW
0
19.7
Twisted Pair Tri-State
Enable, TPTRI
Twisted Pair Signals
are not Tri-Stated or
No effect
Twisted Pair Signals
are Tri-Stated
RW
0
19.6
ICS reserved
Read unspecified
RW
0
19.5
ICS reserved
Read unspecified
RW
0
19.4
ICS reserved
Read unspecified
RW
0
19.3
ICS reserved
Read unspecified
RW
0
1
19.2
ICS reserved
Read unspecified
RW
0
19.1
ICS reserved
Read unspecified
RW
0
19.0
Automatic 100Base-TX
Power Down
Do not automatically
power down
Power down
automatically
RW
1
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