參數(shù)資料
型號(hào)： HC05JJ6GRS
英文描述： 68HC05JJ6 and 68HC05JP6 General Release Specification
中文描述： 68HC05JJ6和68HC05JP6總發(fā)行規(guī)格
文件頁數(shù)： 94/106頁
文件大?。?/td> 1366K
代理商： HC05JJ6GRS
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
B-2
MC68HC05J5A
REV 2.1
STOPMD — STOP Mode Option
1 =
STOP mode is selected.
0 =
STOP mode is converted to HALT mode.
IRQTRIG — IRQ, PA0-PA3 Interrupt Option
1 =
Edge-triggered only.
0 =
Edge-and-level-triggered.
PULLREN — Port A and B Pull-up/down Option
1 =
Connected.
0 =
Disconnected
PAINTEN — PA0-PA3 External Interrupt Option
1 =
External interrupt capability on PA0-PA3 disabled.
0 =
External interrupt capability on PA0-PA3 enabled.
OSCDLY — Oscillator Delay Option
1 =
224 internal clock cycles.
0 =
4064 internal clock cycles.
LVREN — LVR Option
1 =
Low Voltage Reset circuit enabled.
0 =
Low Voltage Reset circuit disabled.
COP_EN — COP Watchdog Timer Option
1 =
Disabled.
0 =
Enabled.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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