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參數(shù)資料
| 型號(hào)： | HC05JJ6GRS |
| 英文描述： | 68HC05JJ6 and 68HC05JP6 General Release Specification |
| 中文描述： | 68HC05JJ6和68HC05JP6總發(fā)行規(guī)格 |
| 文件頁數(shù)： | 63/106頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | HC05JJ6GRS |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
16-BIT TIMER
MOTOROLA
9-5
NOTE
To prevent interrupts from occurring between readings of the ACNTH and ACNTL,
set the I bit in the condition code register (CCR) before reading ACNTH and clear
the I bit after reading ACNTL.
9.3
INPUT CAPTURE REGISTERS
Figure 9-6. Timer Input Capture Block Diagram
The input capture function is a technique whereby an external signal (connected
to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-
ble to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
NOTE
Since the TCAP pin is shared with the PB0 I/O pin, changing the state of the PB0
DDR or Data Register can cause an unwanted TCAP interrupt. This can be
avoided by clearing the ICIE bit before changing the configuration of PB0, and
clearing any pending interrupts before enabling ICIE.
The signal on the TCAP pin is first directed to a schmitt trigger or a voltage
comparator as shown in
Figure 9-8
. Setting the TCAPS bit to “1” will enable the
comparator and the V
DD
/2 reference voltage.
I
ICH ($14)
16-BIT COUNTER
÷
4
INTERNAL
CLOCK
(f
OSC
÷
2)
TIMER1
INTERRUPT
TIMER1 CONTROL REG.
REQUEST
INPUT CAPTURE (ICF)
RESET
ICL ($15)
I
TIMER1 STATUS REG.
$12
$13
INTERNAL
DATA
BUS
(
READ
ICH
READ
ICL
LATCH
I
EDGE
SELECT
& DETECT
LOGIC
I
INTERNAL
DATA
BUS
SIGNAL
CONDITIONING
PB0/
TCAP
TCAPS
(bit7 at $02)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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