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| 型號： | HC05JJ6GRS |
| 英文描述： | 68HC05JJ6 and 68HC05JP6 General Release Specification |
| 中文描述： | 68HC05JJ6和68HC05JP6總發(fā)行規(guī)格 |
| 文件頁數(shù)： | 60/106頁 |
| 文件大小： | 1366K |
| 代理商： | HC05JJ6GRS |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
9-2
16-BIT TIMER
MC68HC05J5A
REV 2.1
The basis of the 16-bit Timer is a 16-bit free-running counter which increases in
count with each internal bus clock cycle. The counter is the timing reference for
the input capture and output compare functions. The input capture and output
compare functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms and timing
delays. Software can read the value in the 16-bit free-running counter at any time
without affect the counter sequence.
Because of the 16-bit timer architecture, the I/O registers are pairs of 8-bit regis-
ters. Each register pair contains the high and low byte of that function. Generally,
accessing the low byte of a specific timer function allows full control of that func-
tion; however, an access of the high byte inhibits that specific timer function until
the low byte is also accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four pres-
caler, the counter rolls over every 262,144 internal clock cycles. Timer resolution
with a 4MHz crystal oscillator is 2 microsecond/count.
The interrupt capability and the input capture edge are controlled by the timer con-
trol register (T1CR) located at $0012 and the status of the interrupt flags can be
read from the timer status register (T1SR) located at $0013.
9.1
TIMER1 COUNTER REGISTERS (TCNTH, TCNTL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in
Figure 9-2
. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
Figure 9-2. 16-Bit Timer Counter Block Diagram
T
TCNTH ($18)
TCNTL LSB
16-BIT COUNTER
÷
4
INTERNAL
CLOCK
(f
OSC
÷
2)
TIMER1 CONTROL REG.
TIMER1
INTERRUPT
REQUEST
OVERFLOW (T1OF)
RESET
TCNTL ($19)
T
TIMER1 STATUS REG.
$12
$13
INTERNAL
DATA
BUS
($FFFC)
READ
TCNTH
READ
TCNTL
READ
LATCH
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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