- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371773 > HC05JJ6GRS 68HC05JJ6 and 68HC05JP6 General Release Specification PDF資料下載
參數(shù)資料
| 型號： | HC05JJ6GRS |
| 英文描述： | 68HC05JJ6 and 68HC05JP6 General Release Specification |
| 中文描述： | 68HC05JJ6和68HC05JP6總發(fā)行規(guī)格 |
| 文件頁數(shù)： | 41/106頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | HC05JJ6GRS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
LOW POWER MODES
MOTOROLA
6-3
STOP Mode. The other option is for the STOP instruction to behave like a WAIT
instruction (except that the restart time will involve a delay) and place the device in
the HALT Mode.
6.1.1 STOP Mode
Execution of the STOP instruction in this mode (selected by a mask option) places
the MCU in its lowest power consumption mode. In the STOP Mode the internal
oscillator is turned off, halting all internal processing, including the COP Watchdog
Timer.
When the CPU enters STOP Mode the interrupt flags (TOF and RTIF) and the
interrupt enable bits (TOFE and RTIE) in the TCSR are cleared by internal hard-
ware to remove any pending timer interrupt requests and to disable any further
timer interrupts. Execution of the STOP instruction automatically clears the I-bit in
the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Sta-
tus Register so that the IRQ external interrupt is enabled. All other registers,
including the other bits in the TCSR, and memory remain unaltered. All input/out-
put lines remain unchanged.
The MCU can be brought out of the STOP Mode only by an IRQ external interrupt
or an externally generated RESET or an LVR reset. When exiting the STOP Mode
the internal oscillator will resume after a 224 or 4064 internal processor clock
cycle oscillator stabilizing delay which is selected by a mask option.
NOTE
Execution of the STOP instruction with the STOP Mode Mask Option will cause
the oscillator to stop and therefore disable the COP Watchdog Timer. If the COP
Watchdog Timer is to be used, the STOP Mode should be changed to the HALT
Mode by choosing the appropriate mask option. See
Section 6.4
for more details.
6.1.2 HALT Mode
Execution of the STOP instruction in this mode (selected by a mask option) places
the MCU in a low-power mode, which consumes more power than the STOP
Mode. In the HALT Mode the internal processor clock is halted, suspending all
processor and internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the timer (MFT or Timer 1) or a reset to be gener-
ated from the COP Watchdog Timer. Execution of the STOP instruction automati-
cally clears the I-bit in the Condition Code Register and sets the IRQE enable bit
in the IRQ Control/Status Register so that the IRQ external interrupt is enabled.
All other registers, memory, and input/output lines remain in their previous states.
The HALT Mode may be terminated by a Timer interrupt, an external IRQ, an LVR
reset, or external RESET occurs. Since the internal timer is still running in the
HALT mode, the wake up delay timer (oscillator stabilizing delay timer) may start
counting from an unknown value. So, the internal processor clock will resume
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HC05K3GRS | 68HC05K3 General Release Specification |
| HC05PL4GRS | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| HC05V7GRS | 68HC05V7 General Release Specification |
| HC05 | Bipolar Transistor; Transistor Polarity:Dual P Channel; Power Dissipation:20W; DC Current Gain Min (hfe):25; Collector Current:1A; DC Current Gain Max (hfe):200; Power (Ptot):20W |
| HC1-5502A-7 | Subscriber Line Interface Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HC05K3GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05K3 General Release Specification |
| HC05PL4GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| HC05V7GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05V7 General Release Specification |
| HC060WE1DS038B | 制造商:TE Connectivity 功能描述:EC7174-000 |
| HC060YW1DS038B | 制造商:TE Connectivity 功能描述:EC7207-000 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。