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參數(shù)資料
| 型號(hào)： | HC05JJ6GRS |
| 英文描述： | 68HC05JJ6 and 68HC05JP6 General Release Specification |
| 中文描述： | 68HC05JJ6和68HC05JP6總發(fā)行規(guī)格 |
| 文件頁數(shù)： | 4/106頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | HC05JJ6GRS |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
ii
MC68HC05J5A
REV 2.1
TABLE OF CONTENTS
Section
Page
4.5.2
4.5.3
4.5.4
OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3) ....................................4-6
TIMER INTERRUPT (MFT).........................................................................4-7
TIMER1 INTERRUPT (16-BIT TIMER)........................................................4-7
SECTION 5
RESETS
EXTERNAL RESET (RESET)..........................................................................5-2
INTERNAL RESETS........................................................................................5-2
POWER-ON RESET (POR) ........................................................................5-2
COMPUTER OPERATING PROPERLY RESET (COPR)...........................5-2
LOW VOLTAGE RESET (LVR)...................................................................5-3
ILLEGAL ADDRESS RESET (ILADR).........................................................5-3
SECTION 6
LOW POWER MODES
STOP INSTRUCTION......................................................................................6-2
STOP Mode.................................................................................................6-3
HALT Mode..................................................................................................6-3
WAIT INSTRUCTION.......................................................................................6-4
DATA-RETENTION MODE..............................................................................6-4
COP WATCHDOG TIMER CONSIDERATIONS .............................................6-4
SECTION 7
INPUT/OUTPUT PORTS
SLOW OUTPUT FALLING-EDGE TRANSITION.............................................7-1
PORT A............................................................................................................7-1
Port A Data Register....................................................................................7-2
Port A Data Direction Register.....................................................................7-2
Port A Pulldown/up Register........................................................................7-3
Port A Drive Capability.................................................................................7-3
Port A I/O Pin Interrupts...............................................................................7-3
PORT B............................................................................................................7-4
Port B Data Register....................................................................................7-4
Port B Data Direction Register.....................................................................7-5
Port B Pulldown/up Register........................................................................7-5
I/O PORT PROGRAMMING ............................................................................7-6
Pin Data Direction........................................................................................7-6
Output Pin....................................................................................................7-6
Input Pin.......................................................................................................7-6
I/O Pin Transitions.......................................................................................7-7
I/O Pin Truth Tables.....................................................................................7-7
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
6.1
6.1.1
6.1.2
6.2
6.3
6.4
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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