參數(shù)資料
型號(hào)： HC05JJ6GRS
英文描述： 68HC05JJ6 and 68HC05JP6 General Release Specification
中文描述： 68HC05JJ6和68HC05JP6總發(fā)行規(guī)格
文件頁(yè)數(shù)： 46/106頁(yè)
文件大?。?/td> 1366K
代理商： HC05JJ6GRS
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
7-2
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC05J5A
REV 2.1
Each Port A pin is controlled by the corresponding bits in a data direction register,
a data register and a pulldown/up register. The Port A Data Register is located at
address $0000. The Port A Data Direction Register (DDRA) is located at address
$0004. The Port A Pulldown/up Register (PDURA) is located at address $0010.
Reset operation will clear the DDRA and the PDURA. The Port A Data Register is
unaffected by reset.
Figure 7-2. Port A I/O Circuitry
7.2.1 Port A Data Register
Each Port A I/O pin has a corresponding bit in the Port A Data Register. When a
Port A pin is programmed as output, the corresponding data register bit deter-
mines the logic state of that pin. When a Port A pin is programmed as input, any
read from the Port A Data Register will return the logic state of the corresponding
I/O pin. The Port A data register is unaffected by reset.
7.2.2 Port A Data Direction Register
Each Port A I/O pin may be programmed as input by clearing the corresponding
bit in the DDRA, or programmed as output by setting the corresponding bit in the
DDRA. The DDRA can be accessed at address $0004. The DDRA is cleared by
reset.
If configured as output pins, PA6 and PA7 have slow output falling-edge transition
feature. The slow transition feature is controlled by the SLOWE bit of DDRB.
SLOWE bit, if set and if the pin is configured as an output pin, enables the slow
falling-edge output transition feature of all four I/O lines, PA6, PA7, PB1, and PB2.
Write $0010
100
μ
A
Pulldown
Read $0000
Write $0000
Read $0004
Data
Register Bit
PA0-PA3 and PA7 only:
to IRQ
interrupt system
8 mA Sink
Capability
(Bits 4-7 Only)
I/O
Pin
Output
Mask Option
(Software Pulldown/up Inhibit)
Internal HC05
Data Bus
Reset
(RST)
Write $0004
Data Direction
Register Bit
Pulldown/up
Register Bit
VDD
5K
Pullup
Note1: All the I/O port pins may have either pullup or pulldown device.
Note2: PA6 and PA7 output drivers are the open-drained type
F
Freescale Semiconductor, Inc.
n
.
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