參數(shù)資料
型號(hào): HC05JJ6GRS
英文描述: 68HC05JJ6 and 68HC05JP6 General Release Specification
中文描述: 68HC05JJ6和68HC05JP6總發(fā)行規(guī)格
文件頁數(shù): 64/106頁
文件大?。?/td> 1366K
代理商: HC05JJ6GRS
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
9-6
16-BIT TIMER
MC68HC05J5A
REV 2.1
Figure 9-7. Timer1 Capture Control Register
TCAPS — Timer Input Capture Comparator Enable
1 =
Timer input capture comparator is selected.
0 =
Timer input capture comparator schmitt trigger is selected.
NOTE
When the comparator and V
DD
/2 reference are enabled, PB0 pin will automatically
becomes an input pin, irrespective of DDR setting. However, it is recommended to
set PB0 as an input first (via DDR), before enabling the comparator. A read of PB0
will reflect the TCAP pin status, not the PB0 register bit.
The comparator uses the V
DD
/2 reference as the compare voltage, resulting in a
typical output as shown in
Figure 9-9
.
Switching off the V
DD
/2 voltage reference by clearing TCAPS=0 will further save
power when the MCU is in a low power mode.
Figure 9-8. TCAP Input Signal Conditioning
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
T1CC
$0002
R
W
TCAPS
reset:
0
0
0
0
0
0
0
0
+
MUX
PB0/
TCAP
Voltage
Reference
V
REF
EN
PB0 I/O
PORT LOGIC
TCAPS bit
V
DD
÷ 2
Schmitt Trigger
Comparator
To edge select and
detect logic
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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