參數(shù)資料
型號： EVAL-ADUC7121QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 83/96頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7121
設(shè)計資源： ADUC7121 Gerber Files
ADUC7121 Schematic
標準包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7121
所含物品： 板，CD
ADuC7121
Data Sheet
Rev. B | Page 84 of 96
FIQVEC Register
The FIQ interrupt vector register, FIQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. Read this register only when an FIQ
occurs and FIQ interrupt nesting has been enabled by setting
Bit 1 of the IRQCONN register.
Name:
FIQVEC
Address:
0xFFFF011C
Default value:
0x00000000
Access:
Read only
Table 119. FIQVEC MMR Bit Designations
Bit
Type
Initial
Value
Description
31:23
Read only
0
Always read as 0.
22:7
Read and
write
0
IRQBASE register value.
6:2
0
Highest priority source. This is a
value between 0 and 27
representing the possible
interrupt sources. For example, if
the highest currently active FIQ is
Timer2, then these bits are
[00100].
1:0
Reserved
0
Reserved bits.
FIQSTAN Register
If IRQCONN.1 is asserted and FIQVEC is read, then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0, then Bit 0 asserts; if Priority 1,
then Bit 1 asserts, and so forth.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example if this register is set to 0x09 then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
FIQSTAN
Address:
0xFFFF013C
Default value: 0x00000000
Access:
Read and write
Table 120. FIQSTAN MMR Bit Designations
Bit
Name
Description
31:8
Reserved
These bits are reserved and should not be
written to.
7:0
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
EXTERNAL INTERRUPTS (IRQ0 TO IRQ5)
The ADuC7121 provides up to six external interrupt sources.
These external interrupts can be individually configured as level
or rising/falling edge triggered.
To enable the external interrupt source, first, the appropriate bit
must be set in the FIQEN or IRQEN register. To select the
required edge or level to trigger on, the IRQCONE register
must be appropriately configured.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the IRQCLRE register.
IRQCONE Register
Name:
IRQCONE
Address:
0xFFFF0034
Default value:
0x00000000
Access:
Read and write
Table 121. IRQCONEMMR Bit Designations
Bit
Value
Name
Description
31:12
Reserved
These bits are reserved and should not be written to.
11:10
11
IRQ5SRC[1:0]
External IRQ5 triggers on falling edge.
10
External IRQ5 triggers on rising edge.
01
External IRQ5 triggers on low level.
00
External IRQ5 triggers on high level.
9:8
11
IRQ4SRC[1:0]
External IRQ4 triggers on falling edge.
10
External IRQ4 triggers on rising edge.
01
External IRQ4 triggers on low level.
00
External IRQ4 triggers on high level.
7:6
11
IRQ3SRC[1:0]
External IRQ3 triggers on falling edge.
10
External IRQ3 triggers on rising edge.
01
External IRQ3 triggers on low level.
00
External IRQ3 triggers on high level.
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