參數(shù)資料
型號(hào)： EVAL-ADUC7121QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/96頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7121
設(shè)計(jì)資源： ADUC7121 Gerber Files
ADUC7121 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7121
所含物品： 板，CD
Data Sheet
ADuC7121
Rev. B | Page 21 of 96
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8 bits, 16 bits, or 32 bits. The length of
the instruction word is 32 bits.
The ARM7TDMI is an ARM7 core with four additional
features, as follows:
T support for the thumb (16-bit) instruction set
D support for debug
M support for long multiplications
I includes the EmbeddedICE module to support
embedded system debugging
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set that has been compressed into
16 bits, called the Thumb instruction set. Faster execution from
16-bit memory and greater code density can usually be achieved
by using the Thumb instruction set instead of the ARM instruc-
tion set, which makes the ARM7TDMI core particularly suitable
for embedded applications.
However, the Thumb mode has two limitations, as follows:
Thumb code typically requires more instructions for the
same job. As a result, ARM code is usually best for
maximizing the performance of time-critical code.
The Thumb instruction set does not include some of the
instructions needed for exception handling, which
automatically switches the core to ARM code for exception
handling.
See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM
and ARM Thumb instruction sets.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra instruc-
tions that perform 32-bit by 32-bit multiplication with a 64-bit
result, and 32-bit by 32-bit multiplication accumulation (MAC)
with a 64-bit result. These results are achieved in fewer cycles
than required on a standard ARM7 core.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and watch-
point registers that allow code to be halted for debugging purposes.
These registers are controlled through the JTAG test port.
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. When in a debug state, the pro-
cessor registers can be inspected, as well as the Flash/EE,
SRAM, and memory mapped registers.
EXCEPTIONS
ARM supports five types of exceptions and a privileged
processing mode for each type. The five types of exceptions are
Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt or FIQ. This is provided to service data
transfers or communication channels with low latency. FIQ
has priority over IRQ.
Memory abort.
Attempted execution of an undefined instruction.
Software interrupt instruction (SWI). This can be used to
make a call to an operating system.
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
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