參數(shù)資料
型號(hào)： EVAL-ADUC7121QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 35/96頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7121
設(shè)計(jì)資源： ADUC7121 Gerber Files
ADUC7121 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7121
所含物品： 板，CD
ADuC7121
Data Sheet
Rev. B | Page 40 of 96
Reset Operation
There are four types of reset: external reset, power-on reset,
watchdog expiration, and software force. The RSTSTA register
indicates the source of the last reset and RSTCLR clears the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset was external. Note that when
clearing RSTSTA, all bits that are currently set to 1 must be
cleared. Otherwise, a reset event occurs.
The RSTCFG register allows different peripherals to retain their
state after a watchdog or software reset.
Table 47. Remap MMR Bit Designations (Address =
0xFFFF0220, Default Value = 0x00)
Bit
Name
Description
0
Remap
Remap bit.
Set by the user to remap the SRAM to Address
0x00000000.
Cleared automatically after reset to remap the
Flash/EE memory to Address 0x00000000.
Table 48. RSTSTA MMR Bit Designations (Address =
0xFFFF0230, Default Value = 0x0X)
Bit
Description
7:3
Reserved.
2
Software reset.
Set by the user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
1
Watchdog timeout.
Set automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
0
Power-on reset.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
RSTCFGKEY0 Register
Name:
RSTCFGKEY0
Address:
0xFFFF0248
Default value:
0xXX
Access
Write
RSTCFGKEY1 Register
Name:
RSTCFGKEY1
Address:
0xFFFF0250
Default value:
0xXX
Access:
Write
Table 49. RSTCFG Write Sequence
Name
Code
RSTCFGKEY0
0x76
RSTCFG
User value
RSTCFGKEY1
0xB1
Table 50. RSTCFG MMR Bit Designations (Address =
0xFFFF024C, Default Value = 0x00)
Bit
Description
7:4
Reserved. Always set to 0.
3
This bit is set to 1 to configure the IDAC outputs to retain
their state after a watchdog or software reset.
This bit is cleared for the IDAC output pins and registers to
return to their default state.
2
This bit is set to 1 to configure the DAC outputs to retain
their state after a watchdog or software reset.
This bit is cleared for the DAC output pins and registers to
return to their default state.
1
Reserved. Always set to 0.
0
This bit is set to 1 to configure the GPIO pins to retain their
state after a watchdog or software reset.
This bit is cleared for the GPIO pins and registers to return
to their default state.
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