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| 型號(hào)： | EVAL-ADUC7121QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 26/96頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 設(shè)計(jì)資源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 32 of 96
Figure 19. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 20), SW3 opens,
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected as soon as
the conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to return the comparator to
a balanced condition. When the comparator is rebalanced, the
conversion is complete.
The control logic generates the ADC output code. The output
impedances of the sources driving the VIN+ input and the VIN
input must be matched; otherwise, the two inputs have different
settling times, resulting in errors.
Figure 20. ADC Conversion Phase
Pseudo Differential Mode
In pseudo differential mode, Channel is linked to the VIN
input of the ADuC7121, and SW2 switches between A
(Channel) and B (VREF). The VIN input must be connected to
ground or a low voltage. The input signal on VIN+ can then vary
from VIN to VREF + VIN. Note that VIN must be chosen so that
VREF + VIN does not exceed AVDD.
Figure 21. ADC in Pseudo Differential Mode
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The VIN input pin can be floating. The input signal
range on VIN+ is 0 V to VREF.
Figure 22. ADC in Single-Ended Mode
Analog Input Structure
Figure 23 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Take care to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. Voltage in excess
of 300 mV causes these diodes to become forward biased and to
start conducting into the substrate. These diodes can conduct
up to 10 mA without causing irreversible damage to the part.
The C1 capacitors in Figure 23 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 100 Ω. The C2 capacitors
are the ADC sampling capacitors and have a capacitance of
16 pF typical.
Figure 23. Equivalent Analog Input Circuit Conversion Phase: Switches Open,
Track Phase: Switches Closed
For ac applications, removing high frequency components from
the analog input signal is recommended with an RC low-pass
filter on the relevant analog input pins. In applications where
harmonic distortion and signal-to-noise ratio are critical, drive
the analog input from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and can necessitate the use of an input buffer amplifier. The choice
of the op amp is a function of the particular application. Figure 24
and Figure 25 give an example of an ADC front end.
Figure 24. Buffering Single-Ended/Pseudo Differential Input
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
09492-
018
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
09492
-019
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN11
VIN–
MUX
CHANNEL+
CHANNEL–
09492
-020
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
CS
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
0949
2-
021
AVDD
C1
D
R1 C2
AVDD
C1
D
R1 C2
09
49
2-
0
22
09
49
2-
0
23
ADuC7121
ADC0
10
0.01F
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