參數(shù)資料
型號(hào): EVAL-ADUC7121QSPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 73/96頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR ADUC7121
設(shè)計(jì)資源: ADUC7121 Gerber Files
ADUC7121 Schematic
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
類(lèi)型: MCU
適用于相關(guān)產(chǎn)品: ADUC7121
所含物品: 板,CD
Data Sheet
ADuC7121
Rev. B | Page 75 of 96
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC7121 integrates a fully programmable logic array (PLA)
that consists of two independent but interconnected PLA blocks.
Each block consists of eight PLA elements, giving each part a
total of 16 PLA elements.
Each PLA element contains a dual input lookup table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 37.
Figure 37. PLA Element
In total, 32 GPIO pins are available on each ADuC7121 for the
PLA. These include 16 input pins and 16 output pins, which need
to be configured in the GPxCON register as PLA pins before using
the PLA. Note that the comparator output is also included as
one of the 16 input pins, and that the JTAG TDI and TDO pins
are included as PLA outputs. If you want to use JTAG program-
ming or debugging, then you cannot use the JTAG TDI and
TDO pins as PLA outputs.
The PLA is configured via a set of user MMRs. The output(s)
of the PLA can be routed to the internal interrupt system, to
the ADC
CONVST signal of the ADC, to an MMR, or to any of the
16 PLA output pins.
The two blocks can be interconnected as follows:
Output of Element 15 (Block 1) can be fed to Input 0 of
Mux 0 of Element 0 (Block 0).
Output of Element 7 (Block 0) can be fed to the Input 0 of
Mux 0 of Element 8 (Block 1).
Table 101. Element Input/Output
PLA Block 0
PLA Block 1
Element
Input
Output
Element
Input
Output
0
P2.7
P3.0
8
P1.4
P3.4
1
P2.2
P3.1
9
P1.5
P3.5
2
P0.6
P3.2
10
P0.5
P3.6
3
P0.7
P3.3
11
P0.4
P3.7
4
P0.1
P1.7
12
P2.1
P0.3
5
P0.0
P1.6
13
P2.0
P0.2
6
P1.1
P2.5
14
P2.3
P1.3
7
P1.0
P2.4
15
P2.6
P1.2
09
49
2-
03
6
4
2
0
1
3
A
B
LOOKUP
TABLE
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