參數(shù)資料
型號： EVAL-ADUC7121QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 77/96頁
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7121
設(shè)計資源： ADUC7121 Gerber Files
ADUC7121 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7121
所含物品： 板，CD
Data Sheet
ADuC7121
Rev. B | Page 79 of 96
INTERRUPT SYSTEM
Table 110. IRQ/FIQ MMRs Bit Designations
Bit
Description
Comments
0
All interrupts OR’ed (FIQ only)
This bit is set if any FIQ is active
1
Software interrupt
User programmable interrupt source
2
Timer0
General-Purpose Timer0
3
Timer1
General-Purpose Timer1
4
Timer2 or wake-up timer
General-Purpose Timer2 or wake-up timer
5
Timer3 or watchdog timer
General-Purpose Timer3 or watchdog timer
6
Timer4
General-Purpose Timer4
7
IDAC fault
IDAC fault IRQ
8
PSM
Power supply monitor
9
Undefined
This bit is not used
10
Flash Control 0
Flash controller for Block 0 interrupt
11
Flash Control 1
Flash controller for Block 1 interrupt
12
ADC
ADC interrupt source bit
13
UART
UART interrupt source bit
14
SPI
SPI interrupt source bit
15
I2C0 Master IRQ
I2C master interrupt source bit
16
I2C0 Slave IRQ
I2C slave interrupt source bit
17
I2C1 Master IRQ
I2C master interrupt source bit
18
I2C1 Slave IRQ
I2C slave interrupt source bit
19
XIRQ0 (GPIO IRQ0 )
External Interrupt 0
20
XIRQ1 (GPIO IRQ1)
External Interrupt 1
21
XIRQ2 (GPIO IRQ2 )
External Interrupt 2
22
XIRQ3 (GPIO IRQ3)
External Interrupt 3
23
PWM
PWM trip interrupt source bit
24
XIRQ4 (GPIO IRQ4 )
External Interrupt 4
25
XIRQ5 (GPIO IRQ5)
External Interrupt 5
26
PLA IRQ0
PLA Block 0 IRQ bit
27
PLA IRQ1
PLA Block 1 IRQ bit
There are 27 interrupt sources on the ADuC7121 that are con-
trolled by the interrupt controller. All interrupts are generated
from the on-chip peripherals, except for the software interrupt
(SWI), which is programmable by the user. The ARM7TDMI
CPU core recognizes interrupts as one of two types only: a
normal interrupt request (IRQ) and a fast interrupt request
(FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is managed
through a number of interrupt related registers. The bits in each
IRQ and FIQ register represent the same interrupt source as
described in Table 110.
The ADuC7121 contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting needs to be enabled by setting the
ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full-vectored interrupt controller is
enabled.
Upon entering the interrupt service routine (ISR), immediately
save IRQSTA/FIQSTA to ensure that all valid interrupt sources
are serviced.
NORMAL INTERRUPT REQUEST (IRQ)
The normal interrupt request (IRQ) is the exception signal
to enter the IRQ mode of the processor. It services general-
purpose interrupt handling of internal and external events.
All 32 bits are logically OR’ed to create a single IRQ signal to the
ARM7TDMI core. The four 32-bit registers dedicated to IRQ
follow.
IRQSIG Register
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is a
read-only register. Do not use this register in an interrupt service
routine for determining the source of an IRQ exception; use
only IRQSTA for this purpose.
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