參數資料
型號： EVAL-ADUC7121QSPZ
廠商： Analog Devices Inc
文件頁數： 82/96頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7121
設計資源： ADUC7121 Gerber Files
ADUC7121 Schematic
標準包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關產品： ADUC7121
所含物品： 板，CD
Data Sheet
ADuC7121
Rev. B | Page 83 of 96
IRQP2 Register
Name:
IRQP2
Address:
0xFFFF0028
Default value: 0x00000000
Access:
Read and write
Table 116. IRQP2 MMR Bit Designations
Bit
Name
Description
31
Reserved
Reserved bit.
30:28
PWMPI
A priority level of 0 to 7 can be set for PWM.
27
Reserved
Reserved bit.
26:24
IRQ3PI
A priority level of 0 to 7 can be set for IRQ3.
23
Reserved
Reserved bit.
22:20
IRQ2PI
A priority level of 0 to 7 can be set for IRQ2.
19
Reserved
Reserved bit.
18:16
IRQ1PI
A priority level of 0 to 7 can be set for IRQ1.
15
Reserved
Reserved bit.
14:12
IRQ0PI
A priority level of 0 to 7 can be set for IRQ0.
11
Reserved
Reserved bit.
10:8
I2C1SPI
A priority level of 0 to 7 can be set for I2C1
slave.
7
Reserved
Reserved bit.
6:4
I2C1MPI
A priority level of 0 to 7 can be set for I2C1
master.
3
Reserved
Reserved bit.
2:0
I2C0SPI
A priority level of 0 to 7 can be set for I2C0
slave.
IRQP3 Register
Name:
IRQP3
Address:
0xFFFF002C
Default value: 0x00000000
Access:
Read and write
IRQP3 MMR Bit Designations
Bit
Name
Description
31:15
Reserved
Reserved bit.
14:12
PLA1PI
A priority level of 0 to 7 can be set for PLA0.
11
Reserved
Reserved bit.
10:8
PLA0PI
A priority level of 0 to 7 can be set for PLA0.
7
Reserved
Reserved bit.
6:4
IRQ5PI
A priority level of 0 to 7 can be set for IRQ5.
3
Reserved
Reserved bit.
2:0
IRQ4PI
A priority level of 0 to 7 can be set for IRQ4.
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits. The first to enable nesting and prioritiza-
tion of IRQ interrupts the other to enable nesting and prioritization
of FIQ interrupts.
If these bits are cleared, then FIQs and IRQs can still be used,
but it is not possible to nest IRQs or FIQs, nor is it possible to
set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Name:
IRQCONN
Address:
0xFFFF0030
Default value: 0x00000000
Access:
Read and write
Table 117. IRQCONN MMR Bit Designations
Bit
Name
Description
31:2
Reserved
These bits are reserved and should not be
written to.
1
ENFIQN
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
0
ENIRQN
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
IRQSTAN Register
If IRQCONN.0 is asserted and IRQVEC is read then one of
these bits is asserted. The bit that asserts depends on the
priority of the IRQ. If the IRQ is of Priority 0 then Bit 0 asserts,
Priority 1 then Bit 1 asserts, and so forth. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09 then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
IRQSTAN
Address:
0xFFFF003C
Default value: 0x00000000
Access:
Read and write
Table 118. IRQSTAN MMR Bit Designations
Bit
Name
Description
31:8
Reserved
These bits are reserved and should not be
written to.
7:0
Setting this bit to 1 enables nesting of FIQ
interrupts.
Clearing this bit means no nesting or
prioritization of FIQs is allowed.
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