參數(shù)資料
型號(hào)： EP7212-CV-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述： 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208
封裝： LQFP-208
文件頁數(shù)： 77/136頁
文件大?。?/td> 2289K
代理商： EP7212-CV-A
EP7212
DS474PP1
77
5.8
CODR — The CODEC Interface Data Register
ADDRESS: 0x8000.0440
The CODR register is an 8-bit read / write register, to be used with the codec interface. This is select-
ed by the appropriate setting of bit 0 (SERSEL) of the SYSCON2 register. Data written to or read from
this register is pushed or popped onto the appropriate 16-byte FIFO buffer. Data from this buffer is
then serialized and sent to or received from the codec sound device. When the codec is enabled, the
codec interrupt CSINT is generated repetitively at 1/8th of the byte transfer rate and the state of the
FIFOs can be read in the system flags register. The net data transfer rate to / from the codec device
is 8 kBytes/s, giving an interrupt rate of 1 kHz.
5.9
5.9.1
UART Registers
UARTDR1–2, UART1–2 Data Registers
ADDRESS: 0x8000.0480 and 0x8000.1480
The UARTDR registers are 11-bit read and 8-bit write registers for all data transfers to or from the
internal UARTs 1 and 2.
Data written to these registers is pushed onto the 16-byte data TX holding FIFO if the FIFO is enabled.
If not it is stored in a one byte holding register. This write will initiate transmission from the UART.
The UART data read registers are made up of the 8-bit data byte received from the UART together
with three bits of error status. If the FIFO is enabled, data read from this register is popped from the
16 byte data RX FIFO. If the FIFO is not enabled, it is read from a one byte buffer register containing
the last byte received by the UART. If it is enabled, data received and error status is automatically
pushed onto the RX FIFO. The RX FIFO is 10-bits wide by 16 deep.
NOTE:
These registers should be accessed as words.
10
9
8
7:0
OVERR
PARERR
FRMERR
RX data
Bit
Description
8
FRMERR
: UART framing error. This bit is set if the UART detected a framing error while receiv-
ing the associated data byte. Framing errors are caused by non-matching word lengths or bit
rates.
PARERR
: UART parity error. This bit is set if the UART detected a parity error while receiving the
data byte.
OVERR
: UART over-run error. This bit is set if more data is received by the UART and the FIFO
is full. The overrun error bit is not associated with any single character and so is not stored in the
FIFO. If this bit is set, the entire contents of the FIFO is invalid and should be cleared. This error
bit is cleared by reading the UARTDR register.
9
10
Table 45. UARTDR1-2 UART1-2
相關(guān)PDF資料
PDF描述
EP7309 HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-CB-C CONN MODULAR JACK 8-8 R/A UNSHLD
EP7309-CR-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-CV-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-ER-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7212-CV-D 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP7230 功能描述:電氣外殼配件 E-PANEL FITS 72 X 30 RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black
EP7236 功能描述:電氣外殼配件 E-PANEL FITS 72 X 36 RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black
EP7309 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309_05 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:High-performance, Low-power, System-on-chip with Enhanced Digital Audio Interface
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*