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參數(shù)資料
| 型號： | EP7212-CV-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| 中文描述： | 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | LQFP-208 |
| 文件頁數(shù)： | 45/136頁 |
| 文件大?。?/td> | 2289K |
| 代理商： | EP7212-CV-A |
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EP7212
DS474PP1
45
to read the byte separately. This is done by reading
the status of two bits in the SYSFLG2 register to
determine the validity of the residual data. These
two bits (RESVAL, RESFRM) are both set high
when a residual is valid. RESVAL is cleared on ei-
ther a new transmission or on reading of the resid-
ual bit by software. RESFRM is cleared only on a
new transmission. By popping the residual byte
into the RX FIFO and then reading the status of
these bits it is possible to determine if a residual bit
has been correctly read.
Figure 10
illustrates this procedure. The sequence
is as follows: read the RESVAL bit, if this is a 0, no
action needs to be taken. If this is a 1, then pop the
residual byte into the FIFO by writing to the
SS2POP location. Then read back the two status
bits RESVAL and RESFRM. If these bits read back
01, then the residual byte popped into the FIFO is
valid and can be read back from the SS2DR regis-
ter. If the bits are not 01, then there has been anoth-
er transmission received since the residual read
procedure has been started. The data item that has
been popped to the top of the FIFO will be invalid
and should be ignored. In this case, the correct byte
will have been stored in the most significant byte of
the next half-word to be clocked into the FIFO.
NOTE:
All the writes / reads to the FIFO are done
word at a time (data on the lower 16 bits is
valid and upper 16 bits are ignored).
Software manually pops the residual byte into the
RX FIFO by writing to the SS2POP location (the
value written is ignored). This write will strobe the
RX FIFO write signal, causing the residual byte to
be written into the FIFO.
Figure 10. Residual Byte Reading
3.13.4.2
Support for Asymmetric Traffic
The interface supports asymmetric traffic (i.e., un-
balanced data flow). This is accomplished through
separate transmit and receive frame sync control
lines. In operation, the receiving node receives a
byte of data on the eight clocks following the asser-
tion of the receive frame sync control line. In a sim-
ilar fashion, the sending node can transmit a byte of
data on the eight clocks following the assertion of
the transmit frame sync pulse. There is no correla-
tion in the frequency of assertions of the RX and
TX frame sync control lines (SSITXFR and
SSIRXFR). Hence, the RX path may bear a greater
data throughput than the TX path, or vice versa.
Both directions, however, have an absolute maxi-
mum data throughput rate determined by the maxi-
mum possible clock frequency, assuming that the
interrupt response of the target OS is sufficiently
quick.
3.13.4.3
Continuous Data Transfer
Data bytes may be sent / received in a contiguous
manner without interleaving clocks between bytes.
The frame sync control line(s) are eight clocks
apart and aligned with the clock representing bit D0
of the preceding byte (i.e., one bit in advance of the
MSB).
3.13.4.4
Discontinuous Clock
In order to save power during the idle times, the
clock line is put into a static low state. The master
is responsible for putting the link into the Idle State.
The Idle State will begin one clock, or more, after
the last byte transferred and will resume at least one
clock prior to the first frame sync assertion. To dis-
able the clock, the TX section is turned off.
In Master mode, the EP7212 does not support the
discontinuous clock.
00
11
01
Residual bit valid
New RX byte received
Pop FIFO
New RX byte
received
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相關(guān)代理商/技術(shù)參數(shù) |
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| EP7212-CV-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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