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參數資料
| 型號： | EP7212-CV-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| 中文描述： | 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | LQFP-208 |
| 文件頁數： | 32/136頁 |
| 文件大?。?/td> | 2289K |
| 代理商： | EP7212-CV-A |
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EP7212
32
DS474PP1
not have an access time greater than 70 ns in order
to meet the 18 MHz timing requirements. When the
internal bus is operating at 36.864 MHz (i.e., for
CPU clock frequencies of 36.864, 49.152, or
73.728 MHz), the DRAM controller will only op-
erate with EDO DRAM. When operating at 36
MHz, the EDO DRAM must not have an access
time greater than 50 ns. The DRAM cycle timings
are adjusted to take advantage of the additional per-
formance available from fast EDO DRAM. In EDO
mode, the EP7212 design relies on the DRAM data
being driven to be available on the external data
bus during the entire high phase of the nCAS signal
so that it can be latched towards the end of the cy-
cle. In Fast Page mode, the data should be latched
at the rising edge of nCAS. It is not possible to use
the EP7212 with fast page mode DRAM at operat-
ing frequencies of 36 MHz or higher.
The DRAM controller breaks all sequential access,
so that the minimum page sizes defined can be sup-
ported. All of the possible page sizes are multiples
of the minimum page size, so by breaking up ac-
cesses on minimum page sizes by default, all ac-
cesses crossing larger page boundaries are broken
up.
Table 16
DRAM Address Mapping for a 32-Bit
DRAM Memory System
shows the address map-
ping for various DRAM’s with square and non-
square row and address inputs. This assumes two
x
16 devices are connected to each RAS line with
32-bit wide DRAM operation selected. This map-
ping is then repeated every 256 Mbytes for each
An example of the DRAM connections for a typical system can be found in
Figure 12. A Maximum EP7212
Based System
on
page 52.
DRAM
Address
Pins
DRAM
Column x16
Mode
DRAM
Column x32
Mode
DRAM
Row x16
Mode
DRAM
Row x32
Mode
7212 Pin Name
0
A1
1
1.
This bit will be generated by the DRAM controller.
A2
A9
A10
A[27]/DRA[0]
1
A2
A3
A10
A11
A[26]/DRA[1]
2
A3
A4
A11
A12
A[25]/DRA[2]
3
A4
A5
A12
A13
A[24]/DRA[3]
4
A5
A6
A13
A14
A[23]/DRA[4]
5
A6
A7
A14
A15
A[22]/DRA[5]
6
A7
A8
A15
A16
A[21]/DRA[6]
7
A8
A9
A16
A17
A[20]/DRA[7]
8
A18
A19
A17
A18
A[19]/DRA[8]
9
A20
A21
A19
A20
A[18]/DRA[9]
10
A22
A23
A21
A22
A[17]/DRA[10]
11
A24
A25
A23
A24
A[16]/DRA[11]
12
A26
A27
A25
A26
A[15]/DRA[12]
Table 15. Physical to DRAM Address Mapping
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EP7212-CV-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7230 | 功能描述:電氣外殼配件 E-PANEL FITS 72 X 30 RoHS:否 制造商:Hammond Manufacturing 產品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black |
| EP7236 | 功能描述:電氣外殼配件 E-PANEL FITS 72 X 36 RoHS:否 制造商:Hammond Manufacturing 產品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black |
| EP7309 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE |
| EP7309_05 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:High-performance, Low-power, System-on-chip with Enhanced Digital Audio Interface |
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