參數(shù)資料
型號: EP7212-CV-A
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述: 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208
封裝: LQFP-208
文件頁數(shù): 100/136頁
文件大?。?/td> 2289K
代理商: EP7212-CV-A
EP7212
100
DS474PP1
tNCSRD
t3
Data in
tPCSRD
t4
t3
Data in
tADRD
t4
t5
t6
t1
Bus held
eXPCLK
nCS[5:0]
nMOE
A[27:0]
WORD
D[31:0]
eXPRDY
Figure 13. Consecutive Memory Read Cycles with Minimum Wait States
NOTES:
1)
tnCSRD = 50 ns at 36.864 MHz
70 ns at 18.432 MHz
120 ns at 13.0 MHz
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 1 MHz), by either driving
EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling
edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock
period where EXPRDY is sampled again. EXPCLK need not be referenced when driving
EXPRDY, but is shown for clarity.
Consecutive reads with sequential access enabled are identical except that the sequential
access wait state field is used to determine the number of wait states, and no idle cycles are
inserted between successive non-sequential ROM/expansion cycles. This improves perfor-
mance so the SQAEN bit should always be set where possible.
tnCSRD = tADRD = tPCSRD
When the EP72xx device implements consecutive reads(e.g., use of the LDM instruction),
regardless of the state of the SQAEN bit, the signals nMOE and nCSx will always remain low
through the entire multi-read access. They will not toggle in-between each different address
access. In order to have these signals toggle, single access read instructions (e.g., LDR) must
be used.
2)
3)
4)
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相關代理商/技術參數(shù)
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