參數(shù)資料
型號： EP7212-CV-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述： 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208
封裝： LQFP-208
文件頁數(shù)： 57/136頁
文件大?。?/td> 2289K
代理商： EP7212-CV-A
EP7212
DS474PP1
57
Table 28. EP7212 Internal Registers (Big Endian Mode)
All internal registers in the IP7212 are reset (cleared to zero) by a system reset (i.e., nPOR, nURESET, or
nPWRFL signals becoming active), except for the DRAM refresh period register (DPFPR), the Real Time
Clock data register (RTCDR), and the match register (RTCMR), which are only reset by nPOR becoming
active. This ensures that the DRAM contents and system time are preserved through a user reset or power
fail condition.
NOTE:
5.1.1
The following Register Descriptions refer to Little Endian Mode Only
PADR Port A Data Register
ADDRESS: 0x8000.0000
Values written to this 8-bit read / write register will be output on Port A pins if the corresponding data
direction bits are set high (port output). Values read from this register reflect the external state of Port
A, not necessarily the value written to it. All bits are cleared by a system reset.
5.1.2
PBDR Port B Data Register
ADDRESS: 0x8000.0001
Values written to this 8-bit read / write register will be output on Port B pins if the corresponding data
direction bits are set high (port output). Values read from this register reflect the external state of Port
B, not necessarily the value written to it. All bits are cleared by a system reset.
5.1.3
PDDR Port D Data Register
ADDRESS: 0x8000.0003
Values written to this 8-bit read / write register will be output on Port D pins if the corresponding data
direction bits are set low (port output). Values read from this register reflect the external state of Port
D, not necessarily the value written to it. All bits are cleared by a system reset.
Big Endian Mode
0x8000.0003
0x8000.0002
0x8000.0001
0x8000.0000
0x8000.0043
0x8000.0042
0x8000.0041
0x8000.0040
0x0000.0080
0X8000.0000
Name
PADR
PBDR
—
PDDR
PADDR
PBDDR
—
PDDDR
PEDR
PEDDR
Default
0
0
RD/WR
RW
RW
—
RW
RW
RW
—
RW
RW
RW
Size
8
8
8
8
8
8
8
8
3
3
Comments
Port A Data Register
Port B Data Register
Reserved
Port D Data Register
Port A data Direction Register
Port B Data Direction Register
Reserved
Port D Data Direction Register
Port E Data Register
Port E Data Direction Register
0
0
0
0
0
0
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