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| 型號： | EP7212-CV-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| 中文描述： | 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | LQFP-208 |
| 文件頁數(shù)： | 69/136頁 |
| 文件大?。?/td> | 2289K |
| 代理商： | EP7212-CV-A |
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EP7212
DS474PP1
69
5.3.3
INTSR2 Interrupt Status Register 2
ADDRESS: 0x8000.1240
This register is an extension of INTSR1, containing status bits for backward compatibility with CL-
PS7111. The interrupt status register also reflects the current state of the new interrupt sources within
the EP7212. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in
Table 35
.
5.3.4
INTMR2 Interrupt Mask Register 2
ADDRESS: 0x8000.1280
This register is an extension of INTMR1, containing interrupt mask bits for the backward compatibility
with the CL-PS7111. Please refer to INTSR2 for individual bit details.
15:14
Reserved
13
12
11:3
2
1
0
URXINT2
UTXINT2
Reserved
SS2TX
SS2RX
KBDINT
Bit
Description
0
KBDINT
: Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the
logical OR of the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the
SYSCON2 register. The interrupt request is latched and can be de-asserted by writing to the
KBDEOI location.
NOTE:
KBDINT is not deglitched.
SS2RX
: Synchronous serial interface 2 receives FIFO half or greater full interrupt. This is gener-
ated when RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX
FIFO is emptied or one SSI2 clock after RX is disabled.
SS2TX
: Synchronous serial interface 2 transmit FIFO less than half empty interrupt. This is gen-
erated when TX FIFO contains fewer than 8 byte pairs. This interrupt gets cleared by loading the
FIFO with more data or disabling the TX. One synchronization clock required when disabling the
TX side before it takes effect.
UTXINT2
: UART2 transmit FIFO half empty interrupt. The function of this interrupt source
depends on whether the UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in
the UART2 bit rate and line control register), this interrupt will be active when there is no data in
the UART2 TX data holding register and be cleared by writing to the UART2 data register. If the
FIFO is enabled, this interrupt will be active when the UART2 TX FIFO is half or more empty and
is cleared by filling the FIFO to at least half full.
URXINT2
: UART2 receive FIFO half full interrupt. The function of this interrupt source depends
on whether the UART2 FIFO is enabled. If the FIFO is disabled, this interrupt will be active when
there is valid RX data in the UART2 RX data holding register and be cleared by reading this data.
If the FIFO is enabled, this interrupt will be active when the UART2 RX FIFO is half or more full or
if the FIFO is non-empty, and no more characters have been received for a three-character time-
out period, t is cleared by reading all the data from the RX FIFO.
1
2
12
13
Table 35. INSTR2
15:14
Reserved
13
12
11:3
2
1
0
URXINT2
UTXINT2
Reserved
SS2TX
SS2RX
KBDINT
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