參數(shù)資料
型號: EP7212-CV-A
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述: 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208
封裝: LQFP-208
文件頁數(shù): 59/136頁
文件大?。?/td> 2289K
代理商: EP7212-CV-A
EP7212
DS474PP1
59
Bit
Description
0:3
Keyboard scan
: This 4-bit field defines the state of the keyboard column drives. The following
table defines these states.
4
TC1M
: Timer counter 1 mode. Setting this bit sets TC1 to prescale mode, clearing it sets free
running mode.
TC1S
: Timer counter 1 clock source. Setting this bit sets the TC1 clock source to 512 kHz, clear-
ing it sets the clock source to 2 kHz.
TC2M
: Timer counter 2 mode. Setting this bit sets TC2 to prescale mode, clearing it sets free
running mode.
TC2S
: Timer counter 2 clock source. Setting this bit sets the TC2 clock source to 512 kHz, clear-
ing it sets the clock source to 2 kHz.
UART1EN
: Internal UART enable bit. Setting this bit enables the internal UART.
5
6
7
8
9
BZTOG
: Bit to drive (i.e., toggle) the buzzer output directly when software mode of operation is
selected (i.e., bit BZMOD = 0). See the BZMOD and BUZFREQ (SYSCON1) bits for more
details.
BZMOD
: This bit selects the buzzer drive mode. When BZMOD = 0, the buzzer drive output pin
is connected directly to the BZTOG bit. This is the software mode. When BZMOD = 1, the buzzer
drive is in the hardware mode. Two hardware sources are available to drive the pin. They are the
TC1 or a fixed internally generated clock source. The selection of which source is used to drive
the pin is determined by the state of the BUZFREQ bit in the SYSCON2 register. If the TC1 is
selected, then the buzzer output pin is connected to the TC1 under flow bit. The buzzer output
pin changes every time the timer wraps around. The frequency depends on what was pro-
grammed into the timer. See the description of the BUZFREQ and BZTOG bits (SYSCON2) for
more details.
10
Table 29. SYSCON1
Keyboard Scan
0
1
2–7
8
9
10
11
12
13
14
15
Column
All driven high
All driven low
All high impedance (tristate)
Column 0 only driven high all others high impedance
Column 1 only driven high all others high impedance
Column 2 only driven high all others high impedance
Column 3 only driven high all others high impedance
Column 4 only driven high all others high impedance
Column 5 only driven high all others high impedance
Column 6 only driven high all others high impedance
Column 7 only driven high all others high impedance
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