參數(shù)資料
型號： EP7212-CV-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述： 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208
封裝： LQFP-208
文件頁數(shù)： 33/136頁
文件大?。?/td> 2289K
代理商： EP7212-CV-A
EP7212
DS474PP1
33
DRAM bank. The placeholder ‘n’ below is equal to
0xC + bank number (i.e., 0xC for bank 0, 0xD for
bank 1).
The DRAM controller contains a programmable re-
fresh counter. The refresh rate is controlled using
the DRAM refresh period register (DRFPR).
The 16/32-bit DRAM selection is made based on
bit 2 of the SYSCON2 register. Both banks must
have the same width.
SYSCON2 0x8000 1100
Bit 2 (DRAMSZ)
0 = 32-bit DRAM
1 = 16-bit DRAM
The default is 32-bit width, since the SYSCON2
register is reset to all zeros on power-up.
3.10
CL-PS6700 PC Card Controller
Interface
Two of the expansion memory areas are dedicated
to supporting up to two CL-PS6700 PC Card con-
troller devices. These are selected by nCS4 and
nCS5 (must first be enabled by bits 5 and 6 of
SYSCON2). For efficient, low power operation,
both address and data are carried on the lower 16
bits of the EP7212 data bus. Accesses are initiated
by a write or read from the area of memory allocat-
ed for nCS4 or nCS5. The memory map within
each of these areas is segmented to allow different
types of PC Card accesses to take place, for at-
tribute, I/O, and common memory space. The CL-
PS6700 internal registers are memory mapped
within the address space as shown in
Table 17
.
NOTE:
Due to the operating speed of the CL-
PS6700, this interface is supported only for
processor speeds of 13 and 18 MHz.
EP7212 Size
Address
Configuration
Total Size
of Bank
Address Range of
Segment(s)
Size of Segment(s)
4 Mbit
9 Row x 9 Column
0.5 Mbyte
n000.0000–n007.FFFF
0.5 MByte
16 Mbit
10 Row x 10 Column
2 Mbytes
n000.0000–n01F.FFFF
2 Mbytes
16 Mbit
12 Row x 8 Column
2 Mbytes
n000.0000–n003.FFFF
n008.0000–n00B.FFFF
n020.0000–n023.FFFF
n028.0000–n02B.FFFF
n080.0000–n083.FFFF
n088.0000–n08B.FFFF
n0A0.0000–n0A3.FFFF
n0A8.0000–n0AB.FFFF
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
64 Mbit
11 Row x 11 Column
8 Mbytes
n000.0000–n07F.FFFF
8 Mbytes
64 Mbit
13 Row x 9 Column
8 Mbytes
n000.0000–n00F.FFFF
n020.0000–n02F.FFFF
n080.0000–n08F.FFFF
n0A0.0000–n0AF.FFFF
n200.0000–n20F.FFFF
n220.0000–n22F.FFFF
n280.0000–n28F.FFFF
n2A0.0000–n2AF.FFFF
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
256 Mbit
12 Row x 12 Column
32 Mbytes
n000.0000–n1FF.FFFF
32 Mbytes
1 Gbit
13 Row x 13 Column
128 Mbytes
n000.0000–n7FF.FFFF
128 Mbytes
Table 16. DRAM Address Mapping When Connected to an External 32-Bit DRAM Memory System
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