參數(shù)資料
型號： EP7212-CV-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述： 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208
封裝： LQFP-208
文件頁數(shù)： 64/136頁
文件大小： 2289K
代理商： EP7212-CV-A
EP7212
64
DS474PP1
5.2.4
SYSFLG1 — The System Status Flags Register
ADDRESS: 0x8000.0140
The system status flags register is a 32-bit read only register, which indicates various system infor-
mation. The bits in the system status flags register SYSFLG1 are defined in
Table 32
.
31:30
VERID
23
UTXFF1
15
CLDFLG
7:4
DID
29
ID
22
28
27
26
BOOTBIT1
21:16
RTCDIV
13
RSTFLG
2
WUDR
BOOTBIT0
23
UTXFF1
12
NBFLG
1
DCDET
SSIBUSY
22
URXFE1
11
UBUSY1
0
MCDR
URXFE1
14
PFFLG
3
WUON
Bit
Description
0
MCDR
: Media changed direct read. This bit reflects the INVERTED non-latched status of the
media changed input.
DCDET
: This bit will be set if a non-battery operated power supply is powering the system (it is
the inverted state of the nEXTPWR input pin).
WUDR
: Wake up direct read. This bit reflects the non-latched state of the wakeup signal.
WUON
: This bit will be set if the system has been brought out of the Standby State by a rising
edge on the wakeup signal. It is cleared by a system reset or by writing to the HALT or STDBY
locations.
DID
: Display ID nibble. This 4-bit nibble reflects the latched state of the four LCD data lines. The
state of the four LCD data lines is latched by the LCDEN bit, and so it will always reflect the last
state of these lines before the LCD controller was enabled.
CTS
: This bit reflects the current status of the clear to send (CTS) modem control input to
UART1.
DSR
: This bit reflects the current status of the data set ready (DSR) modem control input to
UART1.
DCD
: This bit reflects the current status of the data carrier detect (DCD) modem control input to
UART1.
UBUSY1
: UART1 transmitter busy. This bit is set while UART1 is busy transmitting data, it is
guaranteed to remain set until the complete byte has been sent, including all stop bits.
NBFLG
: New battery flag. This bit will be set if a low to high transition has occurred on the
nBATCHG input, it is cleared by writing to the STFCLR location.
RSTFLG
: Reset flag. This bit will be set if the RESET button has been pressed, forcing the
nURESET input low. It is cleared by writing to the STFCLR location.
PFFLG
: Power Fail Flag. This bit will be set if the system has been reset by the nPWRFL input
pin, it is cleared by writing to the STFCLR location.
CLDFLG
: Cold start flag. This bit will be set if the EP7212 has been reset with a power on reset,
it is cleared by writing to the STFCLR location.
1
2
3
4:7
8
9
10
11
12
13
14
15
Table 32. SYSFLG
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