參數(shù)資料
型號： EP7212-CV-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述： 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208
封裝： LQFP-208
文件頁數(shù)： 63/136頁
文件大?。?/td> 2289K
代理商： EP7212-CV-A
EP7212
DS474PP1
63
5.2.3
SYSCON3 System Control Register 3
ADDRESS: 0x8000.2200
This register is an extension of SYSCON1 and SYSCON2, containing additional control for the
EP7212. The bits of this third system control register are defined in
Table 31
.
15
14
13
12
11
10
9
8
Reserved
7
VERSN[2]
Reserved
Reserved
6
VERSN[1]
Reserved
Reserved
5
VERSN[0]
Reserved
Reserved
4
ADCCKNSEN
Reserved
3
DAISEL
Reserved
2
CLKCTL1
DAIEN
1
CLKCTL0
FASTWAKE
0
ADCCON
Bit
Description
0
ADCCON
: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be
used for ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte
SYNCIO(7:0) only is used for compatibility with the CL-PS7111. When this bit = 1, the ADC Con-
figuration Extension field in the SYNCIO register is used for ADC Configuration data and the
value in the ADC Configuration Byte (SYNCIO(6:0)) selects the length of the data (8-bit to 16-bit).
CLKCTL(1:0)
: Determines the frequency of operation of the processor and Wait State scaling.
The table below lists the available options.
1:2
NOTE:
To determine the number of wait states programmed refer to
Table 38
and
Table 39
.
When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from the
default value of ‘00’. Under no circumstances should the CLKCTL bits be changed
using a buffered write.
DAISEL
: When set selects the DAI Interface. This defaults to either the SSI (i.e., DAISEL bit is
low).
ADCCKNSEN
: When set, configuration data is transmitted on ADCOUT at the rising edge of the
ADCCLK, and data is read back on the falling edge on the ADCIN pin. When clear (default), the
opposite edges are used.
VERSN[0:2]
: Additional read-only version bits — will read ‘001’ for Revision C and ‘010’ for Revi-
sion D EP7212 chips.
FASTWAKE
: When set, the device will wake from the Standby State within one to two cycles of
a 4 kHz clock. This bit is cleared at power up, and thus the device first starts using the default
one to two cycles of the 8 Hz clock.
DAIEN
: This bit enables the Digital Audio Interface when set (i.e., when DAIEN is high).
3
4
5:7
8
9
Table 31. SYSCON3
CLKCTL(1:0)
Value
00
01
10
11
Processor
Frequency
18.432 MHz
36.864 MHz
49.152 MHz
73.728 MHz
Memory Bus
Frequency
18.432 MHz
36.864 MHz
36.864 MHz
36.864 MHz
Wait State
Scaling
1
2
2
2
相關(guān)PDF資料
PDF描述
EP7309 HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-CB-C CONN MODULAR JACK 8-8 R/A UNSHLD
EP7309-CR-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-CV-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-ER-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7212-CV-D 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP7230 功能描述:電氣外殼配件 E-PANEL FITS 72 X 30 RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black
EP7236 功能描述:電氣外殼配件 E-PANEL FITS 72 X 36 RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black
EP7309 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309_05 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:High-performance, Low-power, System-on-chip with Enhanced Digital Audio Interface
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*