參數(shù)資料
型號: EP7212-CV-A
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述: 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PQFP208
封裝: LQFP-208
文件頁數(shù): 51/136頁
文件大?。?/td> 2289K
代理商: EP7212-CV-A
EP7212
DS474PP1
51
3.20.2
Functionality
The ICEBreaker module consists of two real-time
watchpoint units together with a control and status
register. One or both of the units can be pro-
grammed to halt the execution of the instructions
by the ARM processor. Execution is halted when
either a match occurs between the values pro-
grammed into the ICEBreaker and the values cur-
rently appearing on the address bus, data bus, and
the various control signals. Any bit can be masked
to remove it from the comparison. Either unit can
be programmed as a watchpoint (monitoring data
accesses) or a breakpoint (monitoring instruction
fetches).
Using one of these watchpoint units, an unlimited
number of software breakpoints (in RAM) can be
supported by substitution of the actual code.
NOTE:
The EXTERN[1:0] signals from the ICE-
Breaker module are not wired out in this
device. This mechanism is used to allow
watchpoints to be dependent on an external
event. This behavior can be emulated in
software via the ICEBreaker control regis-
ters.
A more detailed description is available in the
ARM Software Development Toolkit User Guide
and Reference Manual. The ICEBreaker module
and its registers are fully described in the
ARM7TDMI Data Sheet
.
3.21
A maximum configured system using the EP7212
is shown in
Figure 12
. This system assumes all of
the DRAMs and ROMs are 16-bit wide devices.
The keyboard may be connected to more GPIO bits
than shown to allow greater than 64 keys, however
these extra pins will not be wired into the WAKE-
UP pin functionality.
Maximum EP7212-Based System
Version
Part number
Manufacturer ID
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 25. Device ID Register
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