參數(shù)資料
型號： EP7211
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： 高性能超低功耗系統(tǒng)與LCD控制器芯片
文件頁數(shù)： 96/166頁
文件大小： 2623K
代理商： EP7211
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
96
Register Descriptions
DS352PP3
JUL 2001
5.3.2
INTMR1 Interrupt Mask Register 1
ADDRESS: 0x8000.0280
This interrupt mask register is a 32-bit read/write register, which is used to selectively enable any of
the first 16 interrupt sources within the EP7211. The four shaded interrupts all generate a fast
interrupt request to the ARM720T processor (FIQ), this will cause a jump to processor virtual
address 0000.0001C. All other interrupts will generate a standard interrupt request (IRQ), this will
cause a jump to processor virtual address 0000.00018. Setting the appropriate bit in this register
enables the corresponding interrupt. All bits are cleared by a system reset. Please refer to the INTSR1
register for individual bit details
5.3.3
INTSR2 Interrupt Status Register 2
ADDRESS: 0x8000.1240
This register is an extension of INTSR1, containing status bits for backward compatibility with CL-
PS7111. The interrupt status register also reflects the current state of the new interrupt sources within
the EP7211. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given
below.
7
6
5
4
3
2
1
0
EINT3
EINT2
EINT1
CSINT
MCINT
WEINT
BLINT
EXTFIQ
15
14
13
12
11
10
9
8
SSEOTI
UMSINT
URXINT
UTXINT
TINT
RTCMI
TC2OI
TC1OI
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
SS2TX
SS2RX
KBDINT
15
14
13
12
11
10
9
8
Reserved
Reserved
URXINT2
UTXINT2
Reserved
Reserved
Reserved
Reserved
Bit
Description
0
KBDINT
: Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the logical OR of
the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the SYSCON2 register.
The interrupt request is latched, and can be de-asserted by writing to the KBDEOI location.
NOTE:
KBDINT is not deglitched.
1
SS2RX
: Synchronous serial interface 2 receive FIFO half or greater full interrupt. This is generated when
RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX FIFO is emptied or one
SSI2 clock after RX is disabled.
相關(guān)PDF資料
PDF描述
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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