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| 型號： | EP7211 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| 中文描述： | 高性能超低功耗系統(tǒng)與LCD控制器芯片 |
| 文件頁數(shù)： | 94/166頁 |
| 文件大小： | 2623K |
| 代理商： | EP7211 |
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
94
Register Descriptions
DS352PP3
JUL 2001
5.3
Interrupt Registers
5.3.1
INTSR1 Interrupt Status Register 1
ADDRESS: 0x8000.0240
The interrupt status register is a 32-bit read only register. The interrupt status register reflects the
current state of the first 16 interrupt sources within the EP7211. Each bit is set if the appropriate
interrupt is active. The interrupt assignment is given below.
7
6
5
4
3
2
1
0
EINT3
EINT2
EINT1
CSINT
MCINT
WEINT
BLINT
EXTFIQ
15
14
13
12
11
10
9
8
SSEOTI
UMSINT
URXINT1
UTXINT1
TINT
RTCMI
TC2OI
TC1OI
Bit
Description
0
EXTFIQ
: External fast interrupt. This interrupt will be active if the
NEXTFIQ
input pin is forced low and is
mapped to the FIQ input on the ARM720T processor.
1
BLINT
: Battery low interrupt. This interrupt will be active if no external supply is present (
NEXTPWR
is
high) and the battery OK input pin
BATOK
is forced low. This interrupt is de-glitched with a 16 kHz clock,
so it will only generate an interrupt if it is active for longer than
61
μ
s. It is mapped to the FIQ input on the ARM720T processor and is cleared by writing to the BLEOI
location.
NOTE:
BLINT is disabled during the Standby State.
2
WEINT
: Watch dog expired interrupt. This interrupt will become active on a rising edge of the periodic 64
Hz tick interrupt clock if the tick interrupt is still active (i.e., if a tick interrupt has not been serviced for a
complete tick period). It is mapped to the FIQ input on the ARM720T processor and the TEOI location
NOTE: WEINT is disabled during the Standby State.
Watch dog timer tick rate is 64 Hz (in 13 MHz and 73.728
–
18.432 MHz modes).
NOTE:
Watchdog timer is turned off during the Standby State.
3
MCINT
: Media changed interrupt. This interrupt will be active after a rising edge on the
NMEDCHG
input
pin has been detected, This input is de-glitched with a 16 kHz clock so it will only generate an interrupt if it
is active for longer than 61
μ
s. It is mapped to the FIQ input on the ARM7TDMI processor and is cleared
by writing to the MCEOI location. On power-up, the Media change pin (
NMEDCHG
) is used as an input to
force the processor to either boot from the internal Boot ROM, or from external memory. After power-up,
the pin can be used as a general purpose FIQ interrupt pin.
4
CSINT
: Codec sound interrupt, generated when the data FIFO has reached half full or empty (depending
on the interface direction). It is cleared by writing to the COEOI location.
5
EINT1
: External interrupt input 1. This interrupt will be active if the
NEINT1
input is active (low) it is cleared
by returning
NEINT1
to the passive (high) state.
6
EINT2
: External interrupt input 2. This interrupt will be active if the
NEINT2
input is active (low) it is cleared
by returning
NEINT2
to the passive (high) state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7212 | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7211(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211-CB-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7211-CP-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
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