參數(shù)資料
型號： EP7211
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： 高性能超低功耗系統(tǒng)與LCD控制器芯片
文件頁數(shù)： 119/166頁
文件大?。?/td> 2623K
代理商： EP7211
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
119
Register Descriptions
DS352PP3
JUL 2001
Address: 0x 8000 2000
MCP Control Register: MCCR
Read/Write
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
LBM
ARM
ATM
TRM
TTM
ADM
ECS
MCE
Reset
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
TSD
Res.
ASD
Reset
0
0
Table 5-13. MCP Control Register
Bit
Name
Description
6
–
0
ASD
Audio Sample Rate Divisor
Value (from 6 to 127) used to match the sample rate of the audio codec within the UCB1100 to time
when audio D/A data should be supplied by the audio transmit FIFO.
Sample Rate = (MCP Serial Clock Frequency) /(32 x ASD)
7
—
Reserved
14
–
8
TSD
Telecom Sample Rate Divisor
Value (from 16 to 127) used to match the sample rate of the telecom codec within the UCB1100 to time
when telecom D/A data should be supplied by the telecom transmit FIFO.
Sample Rate = (MCP Serial Clock Frequency) /(32 x TSD)
15
—
Reserved
16
MCE
Multimedia Communications Port Enable
0
—
MCP operation disabled, control of the SIBDIN, SIBDOUT, SIBCLK, and SIBSYNC pins given to
the SSI2/codec/MCP pin mulitiplexing logic to assign I/O pins 60-64 to another block.
1
—
MCP operation enabled
Note that by default, the SSI/CODEC have precedence over the MCP in regard to the use of the I/O
pins. Nevertheless, when Bit 3 (MCPSEL) of register SYSCON3 is set to 1, then the above mentioned
MCP ports are connected to I/O pins 60
–
64.
17
—
Reserved (Always write to zero.)
18
ADM
A/D Data Sampling Mode
0
—
Audio and telecom receive data is stored to their respective FIFOs whenever their receive data
valid bits are valid.
1
—
Audio and telecom receive data is stored when the receive data valid bit is set the first time, and
from that point on whenever the MCP
’
s audio and telecom sample rate counters time-out.
19
TTM
Telecom Transmit FIFO Interrupt Mask
0
—
Telecom transmit FIFO half-full or less condition does not generate an interrupt (TTS bit ignored).
1
—
Telecom transmit FIFO half-full or less condition generates an interrupt (state of TTS sent to inter-
rupt controller).
相關(guān)PDF資料
PDF描述
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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EP7211-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
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