參數(shù)資料
型號: EP7211
廠商: Cirrus Logic, Inc.
英文描述: HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述: 高性能超低功耗系統(tǒng)與LCD控制器芯片
文件頁數(shù): 130/166頁
文件大小: 2623K
代理商: EP7211
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
130
Register Descriptions
DS352PP3
JUL 2001
user must clear set status bits before enabling the MCP. Note that writes to reserved bits are ignored
and reads return zeros.
Figure 5-4. MCP Status Register: MCSR
Address: 0x 8000 2018
MCP Status Register: MCSR
Read/Write &
Read-Only
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TCE
ACE
CRC
CWC
TNE
TNF
ANE
ANF
TRO
TTU
ARO
ATU
TRS
TTS
ARS
ATS
Reset
0
0
0
0
0
1
0
1
0
0
0
0
Table 5-17. MCP Control, Data and Status Register Locations
Bit
Name
Description
0
ATS
Audio Transmit FIFO Service Request Flag (read-only)
0
Audio transmit FIFO is more than half full (five or more entries filled) or MCP disabled
1
Audio transmit FIFO is half full or less (four or fewer entries filled) and MCP operation is
enabled, interrupt request signaled if not masked
(if ATM = 1)
1
ARS
Audio Receive FIFO Service Request (read-only)
0
Audio receive FIFO is less than half full (five or fewer entries filled) or MCP disabled
1
Audio receive FIFO is half full or more (six or more entries filled) and MCP operation is
enabled, interrupt request signaled if not masked (if ARM = 1)
2
TTS
Telecom Transmit FIFO Service Request Flag (read-only)
0
Telecom transmit FIFO is more than half full or less (four or fewer entries filled) or MCP
disabled.
1
Telecom transmit FIFO is half full or less (four or fewer entries filled) and MCP operation is
enabled, interrupt request signaled if not masked
(if TTM = 1)
3
TRS
0
Telecom receive FIFO is less than half full (five or fewer entries filled) or MCP disabled.
1
Telecom receive FIFO is half full or more (six or more entries filled) and MCP operation is
enabled, interrupt request signalled if not masked (if TRM = 1)
4
ATU
Audio Transmit FIFO Underrun
0
Audio transmit FIFO has not experienced an underrun
1
Audio transmit logic attempted to fetch data from transmit FIFO while it was empty, request
interrupt
5
ARO
Audio Receive FIFO Overrun
0
Audio receive FIFO has not experienced an overrun
1
Audio receive logic attempted to place data into receive FIFO while it was full, request
interrupt
相關PDF資料
PDF描述
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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