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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
DS352PP3
JUL 2001
2
OVERVIEW
(cont.)
Power Management
FEATURES
(cont.)
I
ARM720T processor
—
ARM7TDMI CPU
—
8 kbytes of four-way set-associative cache
—
MMU with 64-entry TLB (transition look aside buffer)
—
Write buffer
—
Windows
CE enabled
—
Thumb
code support enabled
I
DRAM controller
—
Supports both 16- and 32-bit-wide DRAMs
—
EDO support (fast page mode support for 13 MHz and
18 MHz operation only)
I
ROM/SRAM/FLASH memory control
—
Decodes 4, 5, or 6 separate memory segments of up to
256 Mbytes each
—
Each segment can be configured as 8, 16, or 32 bits
wide and supports page-mode access
—
Programmable access time for conventional
ROM/SRAM/Flash memory
I
37.5 kbytes of on-chip SRAM for fast program
execution and/or as a frame buffer
I
On-chip ROM; for manufacturing boot-up support
I
Four synchronous serial interfaces
—
ADC (SSI1) Interface: Master mode only; SPI
1
and
Microwire1
2
-compatible (128 kbps operation)
—
SSI2 Interface: Master/Slave mode; SPI/Microwire2
compatible (512 kbps operation)
—
Audio Codec Interface (64 kbps operation)
—
Multimedia Codec Port (Interfaces to Philips
’
UCB1100
The EP7211 is designed for ultra-low-power opera-
tion. Its core operates at only 2.5 V, while its I/O has
an operating range of 2.5 V
–
3.3 V. The device has
three basic power states:
Operating
—
This state is the full performance
state. All the clocks and peripheral logic are
enabled.
Idle
—
This state is the same as the Operating
State, except the CPU clock is halted while wait-
ing for an event such as a key press.
Standby
—
This state is equivalent to the computer
being switched off (no display), and the main
oscillator shut down. An event such as a key
press can wake up the processor.
Memory Interfaces
There are two main external memory interfaces.
The first one is the ROM/SRAM/Flash-style interface
that has programmable wait-state timings and
includes burst-mode capability, with six chip selects
each decoding 256-Mbyte sections of addressable
space. For maximum flexibility, each bank can be
specified to be 8, 16, or 32 bits wide. This allows the
use of 8-bit-wide boot ROM options to minimize over-
all system cost. The on-chip boot ROM can be used
in product manufacturing to serially download system
code into system Flash memory. To further minimize
system memory requirements and cost, the ARM
Thumb
instruction set is supported, providing for the
and UCB1200 codecs) (9.216 Mbps operation)
I
27 bits of general-purpose I/O
—
Three 8-bit and one 3-bit GPIO port
—
Supports scanning keyboard matrix
I
Two UARTs (16550 type)
—
Supports bit rates up to 115.2 kbps
—
Contains two 16-byte FIFOs for TX and RX
—
UART1 supports modem control signals
I
SIR (up to 115.2 kbps) infrared encoder
—
IrDA (Infrared Data Association) SIR protocol encoder
can be optionally switched into TX and RX signals of
UART1
I
PWM interface
—
Provides two 96-kHz clock outputs with programmable
duty ratio (from 1-in-16 to 15-in-16) that can be used to
drive a DC-to-DC converter
I
Two timer counters
I
208-pin LQFP or 256-ball PBGA packages
I
Evaluation kit available with BOM, schematics,
sample code, and design database
I
Support for up to two ultra-low-power CL-PS6700
PC Card controllers
I
Dedicated LED flasher pin from RTC
I
Full JTAG boundary scan and Embedded ICE
support
1
SPI is a registered trademark of Motorola
.
2
Microwire is a registered trademark of National Semiconductor.