參數(shù)資料
型號： EP7211
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： 高性能超低功耗系統(tǒng)與LCD控制器芯片
文件頁數(shù)： 110/166頁
文件大?。?/td> 2623K
代理商： EP7211
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
110
Register Descriptions
DS352PP3
JUL 2001
5.10.4 FBADDR LCD Frame Buffer Start Address
ADDRESS: 0x8000.1000
This register contains the start address for the LCD Frame Buffer. It is assumed that the frame buffer
starts at location 0x0000000 within each chip select memory region. Therefore, the value stored
within the FBADDR register is only the value of the chip select where the frame buffer is located).
On reset, this will be set to 0xC for backward compatibility with the CL-PS7111. Thus the frame
buffer defaults to the start of DRAM Bank 0. The register is 4 bits wide (bits [3:0]). This register
must only be reprogrammed when the LCD is disabled (i.e., setting the LCDEN bit within
SYSCON2 low).
5.11
SSI Register
5.11.1
SYNCIO Synchronous Serial ADC Interface Data Register
ADDRESS: a0x8000.0500
SYNCIO is a 32-bit read/write register. The data written to the SYNCIO register configures the
master only SSI. In default mode, the least significant byte is serialized and transmitted out of the
synchronous serial interface1 (i.e., SSI1) to configure an external ADC, MSB first. In extended
mode, a variable number of bits are sent from SYNCIO[31:16] as determined by the ADC
Configuration Length. The transfer clock will automatically be started at the programmed frequency
and a synchronization pulse will be issued. The
ADCIN
pin is sampled on every positive going clock
edge (or the falling clock edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to
the SYNCIO read register.
During data transfer, the SSIBUSY bit is set high; at the end of a transfer the SSEOTI interrupt will
be asserted. In order to clear the interrupt the SYNCIO register must be read. The data read from the
SYNCIO register is the last sixteen bits shifted out of the ADC.
8
1/2
50.0 %
5.6 %
9
5/9
55.6 %
5.4 %
10
3/5
60.0 %
6.7 %
11
6/9
66.7 %
6.6 %
12
11/15
73.3 %
6.7 %
13
4/5
80.0 %
8.9 %
14
8/9
88.9 %
11.1 %
15
1
100 %
Table 5-12. Grey Scale Value to Color Mapping
(cont.)
Grey Scale Value
Duty Cycle
% Pixels Lit
% Step Change
相關(guān)PDF資料
PDF描述
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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